DRAM Precharge Circuit With Separate Bit and Reference Bit Lines
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Solution Overview
Problem
Traditional 1T1C sensing amplifiers in DRAM experience noise coupling and voltage equalization issues due to shared precharge signals, leading to reduced sensing time and impaired performance.
Innovation Solution
Implementing separate bit line and reference bit line precharge signals to maintain the BLB line at a reference voltage, preventing voltage equalization and enhancing sensing amplifier stability and sensing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a shared precharge signal is used for both bit line and reference bit line, then device complexity is reduced, but noise coupling and voltage equalization occur leading to reduced sensing time and impaired performance
Solution Approach 1:
The patent divides the precharge circuit into two separate precharge circuits: one for the bit line and another for the reference bit line. This segmentation eliminates the shared precharge signal path, preventing noise coupling between the lines while maintaining independent voltage control for each line, thus resolving the contradiction between device complexity and sensing amplifier performance.
2Productivity
If the precharge transistor is disconnected from the bit line during read operation, then sensing operation can proceed, but voltage equalization occurs reducing sensing time
Solution Approach 1:
The patent introduces a reference precharge transistor that acts as an intermediary to maintain the reference bit line voltage during the read operation. While the bit line precharge transistor is disconnected to allow sensing, the reference precharge transistor keeps the reference bit line charged to reference voltage through a reference voltage terminal, preventing voltage equalization and extending the sensing time window.
3Ease of operation
If the reference bit line is allowed to float during read operation, then circuit operation is simplified, but voltage drift towards bit line voltage occurs impairing sensing capability
Solution Approach 1:
The patent applies preliminary action by pre-charging the reference bit line to the reference voltage before the read operation begins and maintaining this charge throughout the sensing period. The reference precharge transistor is activated in advance and remains active during sensing, ensuring the reference bit line voltage is established and maintained at the correct level before and during voltage difference detection, preventing any drift towards the bit line voltage.
Data Source
AI summary
The present disclosure describes a precharge circuit for a memory cell. In an example embodiment, a memory device comprises a memory array including a memory cell, a bit line connected to an output terminal of the memory cell, a reference bit line, and a sensing amplifier circuit coupled to the bit line and coupled to the reference bit line. The memory device further comprises a precharge circuit coupled to the bit line and the reference bit line.