3D Memory Array Layout With Shared Word Lines to Cut Wiring Area
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Solution Overview
Problem
Conventional connection methods in three-dimensional memory devices result in substantial area occupation by wiring and peripheral circuits, undermining the potential for increased density and integration.
Innovation Solution
A semiconductor device design that includes a memory portion, wiring portion, and peripheral circuit portion, where transistors in different sub-memory arrays share a single shared word line, reducing wiring and peripheral circuit area without occupying additional space, and employs a three-dimensional stacked structure with shared bit lines and word lines to enhance integration and density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional connection methods are used in three-dimensional memory devices, then wiring and peripheral circuits can be implemented, but substantial area is occupied by wiring and peripheral circuits
Solution Approach 1:
The patent transitions from planar wiring connections to three-dimensional vertical connections. Word lines and bit lines are extended into the vertical dimension, allowing wiring to connect memory cells across multiple stacked layers without occupying additional lateral area. This dimensional transition resolves the contradiction by maintaining reliable electrical connections while eliminating area occupation.
Solution Approach 2:
The shared word lines serve multiple sub-memory arrays simultaneously, making the wiring structure universal. A single word line can select memory cells across different sub-arrays in different layers, reducing the total number of word lines needed and thereby reducing the overall wiring area while maintaining full functionality.
2Productivity
If memory devices are miniaturized with higher device density, then storage capacity increases, but wiring and peripheral circuits occupy substantial area relative to the reduced device size
Solution Approach 1:
By stacking multiple memory layers vertically and extending word lines and bit lines into the vertical dimension, the patent enables high device density without proportionally increasing wiring area. The wiring structure scales with the memory array in the vertical direction, maintaining area efficiency as density increases.
Solution Approach 2:
Multiple sub-memory arrays share common word lines and bit lines, merging the wiring resources. This sharing approach ensures that wiring area does not increase linearly with the number of memory cells, allowing device density to increase while wiring area remains substantial but not prohibitive.
3Area of stationary object
If shared word lines are used to connect transistors in different sub-memory arrays, then wiring area is reduced, but additional space is not occupied
Solution Approach 1:
The shared word lines are implemented as vertical or three-dimensional structures rather than planar traces. This dimensional approach allows multiple word lines to share physical space in the vertical dimension, reducing lateral wiring area while the complexity is managed through vertical stacking and layering.
Solution Approach 2:
The wiring structure is segmented into multiple layers and levels, with word lines and bit lines organized in distinct vertical stacks. This segmentation allows complex shared wiring to be divided into manageable segments across different layers, reducing the apparent complexity in any single plane while achieving area reduction through vertical integration.
Data Source
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AI summary
Provided are a semiconductor device and a preparation method therefor and an electronic device. The semiconductor device comprises a substrate, and a storage part, a wiring part, and a peripheral circuit part which are arranged on one side of the substrate; the positions of the storage part, the wiring part, and the peripheral circuit part are different in a direction perpendicular to the substrate; the storage part comprises at least two sub-storage arrays, and the at least two sub-storage arrays are sequentially arranged in a first direction parallel to the substrate; each sub-storage array comprises at least one storage unit, and the storage unit comprises a transistor; the wiring part comprises at least one shared word line; and in the at least two sub-storage arrays, the gates of the transistors of the storage units located in different sub-storage arrays are electrically connected to the same shared word line, and the shared word line is connected to the peripheral circuit part.