Clock-Independent Mode Register Setting for Semiconductor Memory
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Solution Overview
Problem
Conventional synchronous semiconductor memory devices are restricted by clock signal frequencies during mode register setting operations, limiting the analysis of tCK margin variations and causing issues with tCK Schmoo analysis, especially as the frequency increases.
Innovation Solution
A clock-independent mode register setting apparatus that uses a mode register setting initiation determination circuit to generate detection signals based on control signal transitions, allowing MRS setting independent of the clock signal, utilizing a data strobe signal with a period greater than or equal to the clock signal to initiate and maintain the MRS mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If mode register setting is performed in synchronization with clock signal, then mode register can be set reliably, but the frequency of test MRS is restricted as clock frequency increases
Solution Approach 1:
The patent introduces a data strobe signal as an intermediary to decouple the mode register setting operation from the clock signal. The data strobe signal serves as a mediator that triggers MRS commands independently of clock edges, allowing test MRS operations to occur at frequencies independent of the operating clock frequency. This resolves the contradiction by enabling reliable MRS setting while eliminating the frequency restriction.
2Measurement precision
If tCK limit is detected before test MRS command application, then timing margin can be analyzed, but desired test mode cannot be set as frequency increases
Solution Approach 1:
The patent implements preliminary action by using the data strobe signal to trigger MRS commands before the tCK limit detection point. By decoupling MRS setting from clock synchronization, the system can perform test mode configuration in advance without being constrained by the upcoming tCK limit detection, enabling both precise timing margin analysis and successful test mode setting even at higher frequencies.
3Productivity
If mode register setting is performed during normal mode operating period, then tCK Schmoo analysis can be carried out, but clock period varies and frequency variations occur
Solution Approach 1:
The patent segments the mode register setting operation from the normal mode operation by using independent data strobe signal triggering. This segmentation allows MRS commands to be issued during any phase of the clock cycle without affecting the clock signal itself, enabling tCK Schmoo analysis to be performed while maintaining stable clock periods and preventing frequency variations during the analysis process.
Data Source
AI summary
Mode register setting methods and apparatuses for semiconductor devices are provided in order to suppress a limit in the frequency at which a mode register of a semiconductor device operates from occurring before the semiconductor device carries out a typical write or read operation, as the frequency at which the semiconductor device operates increases. The mode register setting methods and apparatuses may be applied, for example, to DDR-type semiconductor devices. If a chip selection signal /CS maintains a logic low level for at least a first amount of time, a semiconductor device may initiate a clock-independent mode register setting operation. In the clock-independent mode register setting operation, a mode register set (MRS) command and an MRS code bit may be sampled when the logic level of a data strobe signal applied to the semiconductor device transitions from a logic low level to a logic high level. Therefore, it is possible to solve the problem of restrictions regarding the operating frequency of the mode register of the semiconductor device by performing a test mode register setting operation independent of a clock signal applied to the semiconductor device.