Low Power SRAM Sense Amplifier with Segmented Differential Design
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Solution Overview
Problem
As semiconductor technology advances, increasing device sizes and voltages lead to local device mismatch issues in SRAM memory access circuits, causing performance degradation due to random dopant fluctuation and line edge roughness, which existing sense amplifiers struggle to address effectively.
Innovation Solution
A low power sense amplifier design featuring a pair of pass gate transistors and pull down transistors, along with a current cut-off device, isolates data lines from bit lines, reducing parasitic current and leakage, thereby improving signal integrity and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the area of cross-coupled devices is increased to reduce transistor mismatch, then device matching improves, but switching current and leakage increase
Solution Approach 1:
The sense amplifier is divided into two separate differential amplifiers that operate independently. Each amplifier handles one differential pair, preventing the leakage current from one side from affecting the other. This segmentation allows each amplifier to be optimized for lower leakage while maintaining the necessary transistor matching for reliable operation.
Solution Approach 2:
The parasitic current paths are extracted and removed from the circuit by redesigning the cross-coupled configuration. The patent eliminates the harmful leakage paths that exist in conventional single differential amplifiers while preserving the beneficial transistor matching effects through the segmented architecture.
2Productivity
If device size is reduced to increase devices per IC, then integration density improves, but local device mismatch increases due to random variation
Solution Approach 1:
By segmenting the sense amplifier into two independent differential amplifiers, each amplifier can be designed with smaller transistors to increase integration density. The segmentation ensures that mismatch in one amplifier does not propagate to the other, maintaining overall system reliability despite reduced individual device sizes.
Solution Approach 2:
Each differential amplifier is designed with locally optimized transistor sizing and configuration to achieve the necessary matching for its specific function. This allows different parts of the circuit to have different device characteristics tailored to their local requirements, enabling smaller overall device sizes while maintaining matching quality where needed.
3Power
If conventional sense amplifiers are used to read small signals, then signal amplification is achieved, but parasitic current degrades performance
Solution Approach 1:
The patent converts the potentially harmful parasitic current paths into beneficial features by using them to establish well-defined operating points for the differential amplifiers. The cross-coupled devices that could generate parasitic currents are instead configured to provide stable biasing and improved signal amplification with reduced harmful effects.
Solution Approach 2:
The differential amplifier configuration acts as an intermediary between the memory cell and the output, isolating the signal path from parasitic current paths. This intermediary structure allows the small signals from the memory cell to be amplified while preventing parasitic currents from directly affecting the signal integrity.
Data Source
AI summary
A low power sense amplifier for an SRAM is described. A first pass gate transistor is driven by bit line true and a second pass gate transistor is driven by bit line complement. A first pull down transistor driven by the bit line complement is coupled to the first pass gate transistor, and a second pull down transistor driven by the bit line true is coupled to the second pass gate transistor. A data line true is coupled to a node coupling the first pass gate transistor with the first pull down transistor and a data line complement is coupled to a node coupling the second pass gate transistor with the second pull down transistor. A current cut-off device cuts off parasitic current from flowing through the first pass gate transistor and the first pull down transistor and through the second pass gate transistor and the second pull down transistor.