3D Thyristor Memory Array With Stair Source Lines for Self-Selection
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Solution Overview
Problem
Existing semiconductor memory devices based on thyristors have complex structures and require precise control methods for read, write, and erase operations, with a need for simplified structures and improved control mechanisms.
Innovation Solution
A memory device design featuring gate structures, bit lines, and source lines arranged in a stair-like configuration with sequentially decreasing lengths, utilizing a three-dimensional cross-bar array and thyristor-based memory units controlled by gate voltages, allowing for self-selecting operations without additional selectors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a three-dimensional cross-bar array structure is used with gate structures, source lines and bit lines, then the memory device achieves self-selecting function and high access speeds, but the structure becomes relatively complicated
Solution Approach 1:
The patent transitions from a planar two-dimensional arrangement to a three-dimensional stacked configuration where gate structures are arranged in multiple levels along a vertical direction, with source lines and bit lines forming a cross-bar array in horizontal planes. This dimensional transformation enables self-selecting functionality through the spatial arrangement of components while maintaining compact integration.
2Reliability
If the gate structures, source lines and bit lines are arranged in a cross-bar array to form memory units, then the memory device achieves precise control for read, write and erase operations, but the structure becomes more complicated
Solution Approach 1:
The memory device is segmented into multiple independent gate structures arranged in sequence along a first direction, with each gate structure forming memory units with corresponding channels. The source lines and bit lines are also segmented into multiple sets that intersect to form a cross-bar array. This segmentation allows precise control of individual memory units while organizing the complex structure into manageable, repeating modules.
Solution Approach 2:
The patent employs a three-dimensional arrangement where gate structures are stacked in multiple levels, source lines extend in one direction, and bit lines extend in an orthogonal direction, creating a cross-bar array in the horizontal plane. This spatial organization enables precise control over read, write, and erase operations by selectively activating specific gate-source-bit line combinations, while the modular nature of the cross-bar array prevents excessive complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design achieves high access speeds comparable to random access memory, reduces the number of metal layers required, and effectively controls read, write, and erase operations with minimal sneak currents and erroneous operations.
Implementation Method 1
each memory unit of the memory device is a thyristor. According to the operating characteristics of the thyristors, the current-voltage curve of the memory unit is highly nonlinear, and the memory unit has a very large on-off current ratio, hence the memory device may have a self-selecting function
Data Source
AI summary
A memory device based on thyristors, comprises the following elements. A plurality of gate structures, are continuous structures in the first direction. A plurality of bit lines, extending in a second direction substantially perpendicular to the first direction. A plurality of source lines, extending in the first direction. A plurality of channels, extending in a third direction substantially perpendicular to the first direction and the second direction, and penetrating the gate structures. The first doped regions of the channels are coupled to the bit lines, and the second doped regions of the channels are coupled to the source lines. A plurality of memory units formed by the gate structures and corresponding channels. The source lines are arranged in sequence according to the second direction to form a stair structure, and the lengths of the source lines decrease in sequence in the first direction.