Horizontal 2T0C Memory Cell Layout for Higher DRAM Yield
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Solution Overview
Problem
The manufacturing of semiconductor structures, particularly DRAMs, is hindered by the collapse of capacitors due to increasing aspect ratios, leading to low yield and reduced storage density.
Innovation Solution
A semiconductor structure is designed with first and second transistors extending horizontally parallel to the substrate, forming a 2T0C configuration, which reduces the need for capacitors and optimizes the arrangement of transistor units, improving yield and storage density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the aspect ratio of the capacitor is increased to improve storage density, then the storage density is improved, but the manufacturing difficulty increases and the yield decreases due to capacitor collapse
Solution Approach 1:
The patent transitions from traditional planar capacitor structures to vertical three-dimensional capacitor structures. By stacking capacitors vertically along the third direction perpendicular to the substrate, the design achieves higher storage density without increasing the footprint area, effectively resolving the contradiction between storage density and manufacturing stability
Solution Approach 2:
The patent implements a nested structure where transistor units are stacked vertically with capacitors positioned between adjacent transistor layers. This nested arrangement allows multiple functional layers to occupy the same horizontal footprint, achieving high storage density while maintaining manageable aspect ratios through distributed capacitor placement
2Device complexity
If the number of capacitors is reduced to simplify the structure, then the device complexity is reduced, but the storage capacity may be compromised
Solution Approach 1:
The patent makes the transistor structures serve dual functions: as switching transistors for memory cell operation and as structural supports that define capacitor regions. This multi-functionality reduces the need for separate dedicated capacitor structures while maintaining storage capacity through the vertical stacking architecture
Solution Approach 2:
The patent merges the transistor and capacitor structures into an integrated vertical stack where the transistor units and capacitors are closely coupled in the vertical direction. This merging creates a compact 3D structure that achieves high storage density with simplified process steps compared to separate planar capacitor and transistor fabrication
3Quantity of substance
If transistors are arranged vertically to increase storage density, then the storage density is improved, but the manufacturing precision deteriorates due to alignment difficulties
Solution Approach 1:
The patent forms the vertical transistor stacks and capacitor structures in a predetermined sequence using sequential deposition and etching steps. By establishing the vertical architecture through controlled layer-by-layer fabrication rather than requiring post-fabrication alignment, the design achieves high storage density while maintaining manufacturing precision
Solution Approach 2:
The patent resolves alignment issues by transitioning from horizontal lateral alignment to vertical stacking through controlled deposition. The vertical structures are formed by depositing materials in the third direction perpendicular to the substrate, eliminating the need for precise lateral alignment between stacked components that plagues traditional vertical transistor designs
Data Source
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AI summary
The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof, to solve the technical problem of a low yield of a semiconductor structure. The semiconductor structure includes: a substrate; a memory cell array, located on the substrate, the memory cell array includes a plurality of transistor units, each of the transistor units includes a first transistor and a second transistor extending along a first direction and electrically connected to each other, and the first direction is parallel to the substrate; a first bit line, penetrating the memory cell array and electrically connected to the first transistor; a second bit line, penetrating the memory cell array and electrically connected to the second transistor; a first word line, electrically connected to the first transistor; and a second word line, electrically connected to the second transistor. The first transistor and the second transistor are arranged in a horizontal direction relative to the substrate, which facilitates manufacturing of the first transistor and the second transistor and improves the yield of the semiconductor structure.