On-Die Termination Synchronization for DRAM Signal Integrity
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Solution Overview
Problem
In semiconductor memory systems, the increasing operation speed of dynamic random access memory (DRAM) leads to differences in data transmission delay between various memory modules, causing degradation in data transmission quality due to signal interference and reflection issues.
Innovation Solution
A memory system with a controller that collects delay information from multiple memory devices and adjusts the on-die termination (ODT) parameters to synchronize the ODT duration across different memory devices, ensuring optimal signal integrity by preventing signal reflection and interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the operation speed of DRAM is increased, then the processing capability is improved, but the data transmission delay difference between different memory modules increases, degrading data transmission quality
Solution Approach 1:
The patent implements dynamic ODT duration adjustment where the controller modifies the ODT duration based on real-time delay information collected from different memory modules. This dynamic adaptation allows the system to maintain optimal signal integrity across varying operating conditions and memory module configurations, resolving the contradiction between high-speed operation and data transmission quality.
Solution Approach 2:
The patent changes the ODT duration parameter dynamically based on measured delay information. By adjusting this critical timing parameter according to the actual delay characteristics of different memory modules, the system compensates for propagation delay differences and maintains consistent data transmission quality across all modules regardless of their individual delay characteristics.
2Reliability
If a termination resistor is connected to prevent signal reflection, then signal quality is improved, but device complexity increases due to additional termination circuitry
Solution Approach 1:
The patent merges the termination resistor with the memory device itself, integrating the ODT function into the existing memory chip structure rather than adding separate discrete components. This integration eliminates the need for external termination circuitry while maintaining signal quality, as the memory device internally provides the necessary termination impedance through controlled impedance traces and integrated resistors.
Solution Approach 2:
The memory device provides its own termination function internally without requiring external termination components. The ODT circuit within the memory device automatically adjusts its duration based on delay information, enabling the system to self-compensate for signal reflection issues without adding complexity through external circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents signal integrity degradation by synchronizing ODT parameters across memory devices, enhancing data transmission quality and maintaining signal integrity by ensuring proper impedance matching and reducing unwanted reflections.
Implementation Method 1
The termination resistor can reduce reflection of the data signal and prevent quality degradation of the data signal by matching an external impedance of the memory system with an internal impedance of the memory system
Data Source
AI summary
A memory system includes a first dual in-line memory module (DIMM), a second DIMM, and a controller. The first DIMM may include a first memory device including a first on-die termination (ODT) circuit connected to a data line. The second DIMM may include a second memory device including a second ODT circuit connected to the data line. The controller is connected to the first and second memory devices through the data line, generates first and second delay information, and determines whether to change an ODT duration of the first or second ODT circuit using the first and second delay information. The first delay information is indicative of a time taken for command/address or clock signals to reach the first memory device. The second delay information is indicative of a time taken for command/address signal or clock signals to reach the second memory device.