Memory Read Correction for Ferroelectric Bit Erasure
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Solution Overview
Problem
Ferroelectric memories face issues such as charge sensing retention, leakage, and fatigue, leading to data erasure and reduced reliability.
Innovation Solution
A memory system and device with an integrated correction circuit that performs error detection and correction, including an erasure correction operation, using erasure position information and syndromes to identify and correct erased bit data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If ferroelectric memory is used for high-speed read/write operations and non-volatile storage, then speed and data retention are improved, but erasure occurs due to charge sensing retention issues, leakage, and fatigue
Solution Approach 1:
The patent performs erasure correction operations as a preliminary action during the read process. When erased bit data is detected, the system proactively generates erasure position information and performs syndrome calculations to correct the data before it can cause further reliability issues. This preliminary correction prevents the propagation of erroneous data while maintaining the high-speed read capability of ferroelectric memory.
Solution Approach 2:
The patent implements a feedback mechanism where the read data is analyzed to detect erased bits, and this detection information is fed back to perform corrective operations. The syndrome generator and comparator use the detected erasure positions to calculate syndromes and determine whether correction is needed, creating a closed-loop feedback system that maintains data integrity without sacrificing read speed.
2Reliability
If erasure correction operations are performed to correct erased bit data, then data integrity is improved, but device complexity increases due to additional correction circuits and operations
Solution Approach 1:
The patent merges the erasure correction functionality with the existing read circuitry. The erasure position detector, syndrome generator, and data corrector are integrated into the memory read path, allowing erasure correction to be performed using the same operational framework as normal read operations. This merging reduces the need for completely separate correction circuits and minimizes overall device complexity.
Solution Approach 2:
The correction circuit is designed with multi-functionality to handle both error detection and erasure correction operations using the same hardware resources. The syndrome generator can operate in different modes depending on whether error correction or erasure correction is needed, and the data corrector can apply different correction algorithms based on the type of data degradation detected. This universality reduces the need for dedicated circuits for each function.
3Manufacturing precision
If erasure position information and syndromes are generated and compared to correct erased bits, then manufacturing precision is improved, but loss of time increases due to additional processing steps
Solution Approach 1:
The patent applies partial action by performing erasure correction only when erased bit data is actually detected during the read operation. The system uses an erasure position detector to identify the presence of erased bits, and only then proceeds with generating erasure position information and performing syndrome calculations. This selective approach avoids the time penalty of always performing full correction operations, while still achieving high correction precision when needed.
Solution Approach 2:
The system performs preliminary detection of erased bits using the erasure position detector before committing to full correction operations. This preliminary action allows the system to quickly identify whether correction is needed and prepare the necessary erasure position information in advance, reducing the overall time penalty by avoiding unnecessary correction steps for clean data.
Data Source
AI summary
An operating method of a memory device includes reading, from a memory cell array in the memory device, read data including at least one piece of erased bit data, generating erasure position information based on the read data, generating a partial syndrome associated with non-erased bit data of the read data, based on the erasure position information, an H-matrix, and the read data, generating, based on the erasure position information and the H-matrix, an erasure syndrome set associated with the at least one piece of erased bit data and including a plurality of erasure syndromes, determining whether an erasure syndrome identical to the partial syndrome is present in the erasure syndrome set, and generating corrected data by correcting the read data based on the erasure syndrome identical to the partial syndrome.