7T Memory Cell Dynamic Voltage Control for Write Power Reduction
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Solution Overview
Problem
Existing memory cells, such as 8T cells, face challenges in maintaining read and write stability while reducing power consumption, especially in high-density SRAM designs, as they consume more power and increase memory cell size when row-biasing is implemented.
Innovation Solution
A 7T memory cell design is introduced, which includes two cross-coupled inverters and a pass gate for write operations, utilizing a source bias along the row direction to enable lower power consumption during write operations by varying power supply voltages, allowing for efficient implementation with only one access transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If 8T memory cells are used to maintain read and write stability, then stability is improved, but power consumption increases
Solution Approach 1:
The patent applies parameter changes by varying the power supply voltage to the second inverter during write operations. Specifically, the voltage at the second power supply voltage terminal is varied relative to the first power supply voltage terminal, enabling dynamic control of power consumption while maintaining write stability. This resolves the contradiction by allowing the memory cell to operate with lower power during writes without sacrificing reliability.
2Use of energy by moving object
If row-biasing is implemented in 8T cells to lower power consumption, then power consumption is reduced, but memory cell size increases
Solution Approach 1:
The patent extracts the row-biasing functionality from the traditional 8T cell structure and implements it selectively in a 7T cell configuration. By using a 7T cell with one less transistor than the conventional 8T cell, the patent reduces the memory cell area while still achieving lower power consumption through selective application of biased write operations using the varied power supply voltage to the second inverter.
3Area of stationary object
If 6T memory cells are used for high-density designs, then area is reduced, but read and write stability becomes difficult to maintain
Solution Approach 1:
The patent enhances the 6T cell structure by adding a seventh transistor and implementing varied power supply voltage to the second inverter. This parameter change approach allows the memory cell to maintain smaller area comparable to 6T cells while achieving improved write stability through dynamic voltage control during write operations, thus resolving the stability issue without sacrificing high-density design benefits.
Data Source
AI summary
A memory cell including an access transistor coupled to a first storage node and a read port coupled to one of the first storage node or a second storage node is provided. The memory cell further includes a first inverter having an input terminal coupled to the first storage node, an output terminal, and a first power supply voltage terminal for receiving a first power supply voltage. The memory cell further includes a second inverter having an input terminal coupled to the output terminal of the first inverter, an output terminal coupled to the input terminal of the first inverter at the first storage node, and a second power supply voltage terminal for receiving a second power supply voltage, wherein the second power supply voltage is varied relative to the first power supply voltage during a write operation to the memory cell.