3D DRAM Memory Cell With Vertical TFET for Leakage Control
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Solution Overview
Problem
The increasing demand for high integration in semiconductor memory devices leads to reduced transistor sizes, which results in increased leakage current, necessitating improved performance and reliability.
Innovation Solution
A semiconductor memory device design featuring a DRAM structure with two transistors, including a first transistor with a three-dimensional channel structure and a second transistor with a vertical channel tunneling FET structure, where the second transistor is used as a write transistor and the first as a read transistor, to reduce leakage current and enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size is reduced to achieve high integration, then device density is improved, but leakage current increases
Solution Approach 1:
The patent introduces a vertical channel structure for the second transistor, transitioning from a planar two-dimensional channel to a three-dimensional vertical channel. This dimensional change allows the transistor to achieve better gate control and reduced leakage current while maintaining a compact footprint, thus resolving the contradiction between high integration density and leakage current control.
Solution Approach 2:
The patent changes the channel orientation parameter from horizontal to vertical, and modifies the transistor structure parameters by stacking the second transistor on top of the first transistor. These parameter changes enable the device to maintain high density while achieving lower leakage current through improved gate control in the vertical channel configuration.
2Area of stationary object
If transistor size is reduced to achieve high integration, then area is reduced, but performance deteriorates
Solution Approach 1:
By stacking transistors vertically and using a vertical channel structure, the patent utilizes the third dimension (height) to pack more functionality into a smaller planar area. This allows the memory cell to maintain small area while preserving or enhancing performance through the improved characteristics of the vertical channel transistor.
Solution Approach 2:
The patent implements a nested structure where the second transistor is stacked on top of the first transistor, with the pillar structure containing the vertical channel nested within the overall memory cell architecture. This nesting approach maximizes space utilization and maintains small area while achieving high performance through the vertical channel transistor.
3Ease of manufacture
If conventional transistor structure is used, then manufacturing is simple, but leakage current control is poor
Solution Approach 1:
The patent extends the conventional planar manufacturing process into the vertical dimension by forming a vertical channel through epitaxial growth and selective doping. While this adds complexity compared to simple planar transistors, the vertical structure provides superior leakage control, achieving a balance between manufacturability and performance.
Solution Approach 2:
The patent applies different structural configurations to different transistors within the same memory cell - the first transistor uses a conventional planar structure while the second transistor uses a vertical channel structure. This local differentiation allows optimization of each transistor's function while maintaining overall manufacturability through established semiconductor fabrication techniques.
Data Source
AI summary
A semiconductor memory device includes a plurality of memory cells arranged on a substrate. Each of the plurality of memory cells may include a first transistor on the substrate and a second transistor on the first transistor. The first transistor may include a first channel region between a first source region and a first drain region, a first gate electrode, and a first gate insulating layer. The second transistor may include a pillar structure having a second drain region, a second channel region and a second source region sequentially stacked on the first gate electrode, a second gate electrode on one side of the second channel region, and a second gate insulating layer between the second channel region and the second gate electrode. the second drain region and the second source region may have a first conductivity type impurity region and a second conductivity type impurity region, respectively.