Bit Line Multiplexer Circuit for Low-Delay Memory Read and Write
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices face challenges in reducing bit line loading, read delay, and read energy without increasing the periphery area and leakage, particularly in multiplexing operations of MRAM devices.
Innovation Solution
A write-read circuit with a multiplexer that divides select devices into read and write parts, using smaller read transistors and maintaining sufficient write current, and includes a second multiplexer for reference bit lines to manage capacitive loading during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If larger multiplexer dimensions are used to meet higher write current requirements, then write current is sufficient, but bit line loading increases leading to increased read delay and read energy
Solution Approach 1:
The select device is segmented into two separate transistors: a first transistor optimized for read operations with smaller dimensions to reduce capacitive loading, and a second transistor that provides additional write current capability. This segmentation allows each transistor to be independently optimized for its specific function, resolving the contradiction between write current requirements and read delay.
2Power
If larger multiplexer dimensions are used to meet higher write current requirements, then write current is sufficient, but periphery area increases leading to increased leakage
Solution Approach 1:
By dividing the select device into two transistors with different optimization goals, the overall periphery area is better utilized. The first transistor uses minimal area sufficient for read operations, while the second transistor adds write current capability without requiring a complete redesign of the multiplexer structure, thus controlling total area growth and associated leakage.
3Loss of time
If smaller multiplexer dimensions are used to decrease bit line loading, then read delay and read energy are reduced, but write current becomes insufficient
Solution Approach 1:
The circuit dynamically activates different transistor combinations based on operation type. During read operations, only the first transistor is activated with optimized dimensions for low capacitive loading. During write operations, both transistors are activated to provide sufficient write current. This dynamic switching allows the system to adapt its effective size and current capability to the operational requirements.
4Power
If larger multiplexer dimensions are used to meet higher write current requirements, then write current is sufficient, but read energy increases due to higher bit line loading
Solution Approach 1:
The segmented select device structure with the first transistor optimized for read operations minimizes capacitive loading on bit lines during reads, directly reducing read energy consumption. The second transistor is only activated during write operations, so it does not contribute to read energy. This segmentation effectively decouples write current capability from read energy consumption.
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
The present disclosure relates to memory devices, in particular, to memory devices with multiplexers for multiplexing write and read operations to bit lines. A write-read circuit of this disclosure comprises a multiplexer for multiplexing the write and read operations. The multiplexer comprises a plurality of select devices, each select device being associated with one of a plurality of bit lines, and each select device comprising a first transistor and a second transistor. The write-read circuit further comprises a controller configured to, for a write operation using a particular bit line, controlling the multiplexer to turn on both transistors of the first select device associated with the particular bit line, and for a read operation using the particular bit line, to control the multiplexer to turn on the first transistor and turn off the second transistor of the first select device associated with the particular bit line.