Asynchronous Memory Interface Using Repurposed DDR Pins
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Solution Overview
Problem
Existing memory systems using synchronous DDR protocols are inadequate for supporting transactional interfaces with non-volatile and volatile memories, as they lack the necessary asynchronous communication capabilities to handle variable timings and provide device feedback to memory controllers.
Innovation Solution
The implementation of an asynchronous communication protocol that repurposes pins of a DDR memory channel to enable asynchronous data transmission and device feedback between memory controllers and modules containing non-volatile and volatile memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If synchronous DDR protocol is used, then timing control is simplified, but device feedback capability is limited
Solution Approach 1:
The patent makes DDR memory pins serve dual purposes: during synchronous operations they handle data transfer with fixed timing, while during asynchronous operations they transmit device feedback and variable-timing data. This multi-functionality allows the same physical interface to support both synchronous DDR protocol and asynchronous transactional interfaces without requiring separate dedicated feedback pins.
Solution Approach 2:
The patent introduces dynamic timing adjustments where the memory interface can switch between fixed synchronous timing and variable asynchronous timing based on operational needs. The system dynamically adapts timing parameters to accommodate different memory types (volatile and non-volatile) and operational modes, enabling flexible feedback transmission while maintaining compatibility with standard DDR protocols.
2Loss of information
If asynchronous communication protocol is implemented, then device feedback capability is improved, but timing complexity increases
Solution Approach 1:
The patent makes DDR memory pins serve dual purposes: during synchronous operations they handle data transfer with fixed timing, while during asynchronous operations they transmit device feedback and variable-timing data. This multi-functionality allows the same physical interface to support both synchronous DDR protocol and asynchronous transactional interfaces without requiring separate dedicated feedback pins.
Solution Approach 2:
The patent introduces an intermediary control mechanism that manages the transition between synchronous and asynchronous modes. This intermediary layer handles the complexity of timing coordination, protocol switching, and feedback interpretation, shielding the main memory controller from direct exposure to timing complexities while enabling comprehensive device feedback capabilities.
3Adaptability or versatility
If non-volatile and volatile memories are co-located, then memory channel utilization is improved, but communication protocol compatibility becomes difficult
Solution Approach 1:
The patent introduces dynamic timing adjustments where the memory interface can switch between fixed synchronous timing and variable asynchronous timing based on operational needs. The system dynamically adapts timing parameters to accommodate different memory types (volatile and non-volatile) and operational modes, enabling flexible feedback transmission while maintaining compatibility with standard DDR protocols.
Solution Approach 2:
The patent introduces an intermediary control mechanism that manages the transition between synchronous and asynchronous modes. This intermediary layer handles the complexity of timing coordination, protocol switching, and feedback interpretation, shielding the main memory controller from direct exposure to timing complexities while enabling comprehensive device feedback capabilities.
4Device complexity
If repurposed pins are used for asynchronous data, then additional feedback pins are eliminated, but signal interference risk increases
Solution Approach 1:
The patent employs periodic time-division multiplexing where repurposed pins alternate between synchronous data transmission and asynchronous feedback transmission in regularly spaced time slots. This periodic switching ensures that synchronous and asynchronous signals do not overlap in time, preventing signal interference while allowing the same physical pins to carry both types of data throughout the operational cycle.
Data Source
AI summary
A memory module that includes a non-volatile memory and an asynchronous memory interface to interface with a memory controller is presented. The asynchronous memory interface may use repurposed pins of a double data rate (DDR) memory channel to send an asynchronous data to the memory controller. The asynchronous data may be device feedback indicating a status of the non-volatile memory.