Interleaved Word Line Layout to Prevent Memory Read Disturbance
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Solution Overview
Problem
Conventional memory arrays suffer from 'dummy read' events and read/write disturbances due to shared word lines, leading to increased power consumption and device failure risks.
Innovation Solution
Implementing memory arrays with interleaved word lines, where adjacent memory cells in a row do not share a word line, using at least two word lines coupled to alternating memory cells to prevent adjacent cells from being partially activated during operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If shared word lines are used in conventional memory arrays, then device complexity is reduced, but dummy read events and read/write disturbances occur leading to increased power consumption and device failure risks
Solution Approach 1:
The patent divides the memory array into multiple independent sub-arrays, each with its own dedicated word lines. This segmentation prevents disturbances in one sub-array from affecting adjacent cells in other sub-arrays, eliminating dummy read events and reducing device failure risk while maintaining manageable complexity through modular organization.
2Ease of manufacture
If shared word lines are used in conventional memory arrays, then manufacturing is simplified, but power consumption increases due to dummy read events
Solution Approach 1:
By segmenting the memory array into independent sub-arrays with dedicated word lines, the patent eliminates dummy read events where activated word lines inadvertently read adjacent cells. This reduces unnecessary power consumption during read operations while the modular segmented structure remains compatible with standard semiconductor manufacturing processes.
3Reliability
If interleaved word lines are implemented, then read/write disturbances are minimized, but device complexity increases
Solution Approach 1:
The patent segments the memory array into independent sub-arrays with dedicated word lines, which eliminates read/write disturbances by preventing activated word lines from affecting adjacent cells. The segmentation approach maintains reasonable device complexity through modular organization and systematic interconnection of sub-arrays.
Solution Approach 2:
The patent extends the word line structure into multiple dimensions by creating interleaved sets of word lines (first set, second set, third set) that operate in different spatial dimensions. This dimensional expansion allows simultaneous access to multiple sub-arrays while maintaining isolation between adjacent cells, improving reliability without excessive complexity increase.
4Reliability
If interleaved word lines are implemented, then adjacent cells are prevented from partial activation, but manufacturing complexity increases
Solution Approach 1:
The patent segments the memory array into independent sub-arrays with dedicated word lines, ensuring that activation of one word line only affects cells within its own sub-array. This prevents partial activation of adjacent cells while using standard segmented fabrication techniques compatible with existing manufacturing processes.
Data Source
AI summary
A memory system includes a first column of memory cells coupled to a first word line and a second a second column of memory cells coupled to a second word line. A first memory cell of the first column is in the same row as a second memory cell of the second column. The memory system includes a word line driver circuit configured to generate a select signal at the first word line to select the first memory cell and de-select the second memory cell.