SOT-MRAM Row Layout for Concurrent Read-Write Without Interference
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Solution Overview
Problem
Existing MRAM technologies face challenges in efficiently performing concurrent writing and reading operations in a matrix of Spin-Orbit Torque MRAM (SOT-MRAM) cells, leading to inefficiencies and potential interference between writing and reading modes.
Innovation Solution
The implementation of a matrix structure for SOT-MRAM cells, where each row operates in either writing or reading mode, with specific bit lines and sense amplifiers configured to detect voltage changes on read bit lines during charging or discharging, allowing simultaneous concurrent writing and reading operations without interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If concurrent writing and reading operations are performed in existing MRAM technologies, then operational efficiency is improved, but interference between writing and reading modes occurs
Solution Approach 1:
The MRAM array is segmented into multiple independent banks, where each bank can independently perform writing or reading operations. This segmentation allows concurrent operations across different banks without interference, as each bank operates autonomously with its own word lines and bit lines.
Solution Approach 2:
Sense amplifiers are introduced as intermediary components between the bit lines and the readout circuitry. These sense amplifiers detect voltage changes on bit lines during reading operations while being electrically isolated from the writing operations, thereby mediating between read and write processes to prevent direct interference.
2Productivity
If multiple operations are performed simultaneously in a matrix of SOT-MRAM cells, then throughput is improved, but control complexity increases
Solution Approach 1:
The system dynamically configures the operational mode of each bank based on demand, allowing flexible switching between writing and reading modes. Word lines and bit lines are dynamically allocated to different banks as needed, enabling efficient concurrent operations without requiring a static, overly complex control structure.
Solution Approach 2:
The same word lines and bit lines are used for both writing and reading operations across different banks. This multi-functionality reduces the need for separate dedicated lines for each operation type, thereby controlling complexity while enabling concurrent operations through bank-level multiplexing.
3Measurement precision
If sense amplifiers detect voltage changes during bit line charging, then reading precision is improved, but power consumption increases
Solution Approach 1:
Bit lines are pre-charged to a predetermined voltage level before reading operations begin. This preliminary action prepares the bit lines for accurate voltage change detection by sense amplifiers, ensuring that the voltage differential caused by reading a cell is clearly distinguishable from noise, thereby improving reading precision while allowing the sense amplifier to operate efficiently.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient and concurrent writing and reading of data in SOT-MRAM cells, reducing operational conflicts and enhancing the overall performance and efficiency of the memory device.
Implementation Method 1
The resistance of the magnetic tunnel junction depends upon the relative alignment of the magnetization of the two ferromagnetic layers
Implementation Method 2
the flow of an electric current through the conductive layer generates a spin-orbit torque which is used to manipulate a magnetic state of the magnetic tunnel junction of the memory cell
Data Source
AI summary
In a matrix of SOT-MRAM cells, a first row is selected for writing and a second row is selected for reading. A first SOT-MRAM cell of the first row and a second SOT-MRAM of the second row are in a first column, while a third SOT-MRAM cell of the first row and a fourth SOT-MRAM of the second row are in a second column. The currents for writing the first SOT-MRAM cell and the third SOT-MRAM cell are in opposite direction. A first sense amplifier is configured to detect a voltage change on the first read bit line which is charged with a first read current in the second SOT-MRAM cell. A second sense amplifier is configured to detect a voltage change on the second read bit line which is discharged with a second read current in a fourth SOT-MRAM cell.