Capacitive Memory Cell Readout With Bitline Precharge
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Solution Overview
Problem
The high plateline read voltage required to compensate for parasitic capacitances in capacitive memory cells increases stress on the memory elements and access devices, reducing durability and potentially leading to read errors due to a narrowed memory window.
Innovation Solution
Charging the bitline to a base voltage during plateline charging to cancel the contribution from parasitic capacitances, allowing for a lower plateline read voltage and reducing stress on memory elements, thereby maintaining a larger read window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high plateline read voltage is applied to compensate for parasitic capacitances, then the read accuracy is improved, but the stress on memory elements and access devices increases, reducing durability
Solution Approach 1:
The patent applies preliminary anti-action by charging the bitline to a base voltage before the plateline read voltage is applied. This pre-charging creates an opposing voltage effect that counteracts the parasitic capacitance influence, allowing for accurate reading without requiring excessive plateline voltage that would stress the memory elements.
Solution Approach 2:
The patent implements preliminary action by preparing the bitline in advance with a base voltage charge during a setup phase before the actual read operation. This preliminary preparation ensures that when the plateline voltage is applied, the bitline is already in the optimal state to detect voltage changes without being overwhelmed by parasitic effects, thereby enabling lower read voltages.
2Difficulty of detecting and measuring
If a high plateline read voltage is applied to overcome parasitic capacitance effects, then the signal detection capability is improved, but the memory window narrows, leading to read errors
Solution Approach 1:
By pre-charging the bitline to a base voltage, the system creates a reference state that opposes the parasitic capacitance charging effect. This allows the actual memory signal to be detected with higher contrast and accuracy using lower plateline voltages, preventing memory window narrowing while maintaining strong signal detection capability.
Solution Approach 2:
The patent changes the voltage parameter timing and sequence - specifically applying bitline base voltage before plateline read voltage - to optimize the detection process. This parameter sequencing allows the system to achieve better signal-to-noise ratio at lower overall voltage levels, preserving the memory window while enhancing signal detection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains a larger read window and reduces stress on memory elements, enhancing durability and accuracy in reading capacitive memory cells.
Implementation Method 1
additional, non-selected memory cells (i.e., memory cells having their access device closed) may also be connected to the plateline and to the bitline the selected memory cell is connected to. Each of these non-selected memory cells may provide a parasitic capacitance between the plateline and the bitline
Data Source
AI summary
Various aspects relate to a memory cell arrangement including: bitlines; wordlines; platelines; capacitive memory cells, wherein each of the capacitive memory cells is connected to and selectively addressable via a corresponding bitline, a corresponding wordline, and a corresponding plateline; a read-out circuit configured to carry out a read-out operation to read a memory state of a capacitive memory cell of the capacitive memory cells by addressing the capacitive memory cell via its corresponding bitline, corresponding wordline, and corresponding plateline, the read-out operation including: applying a base voltage at the corresponding bitline during charging the corresponding plateline to a predefined plateline read voltage value; after the plateline voltage is charged to the predefined plateline read voltage value, applying a wordline voltage at the corresponding wordline to thereby charge the corresponding bitline to a characteristic voltage; and determining the memory state of the capacitive memory cell based on sensing the characteristic voltage.