Memory Write Current Copy Circuit for Stable Cell Programming

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Solution Overview

Problem

Existing memory systems face challenges in stably supplying the necessary current for write operations in resistance change type memory elements integrated on semiconductor substrates.

Innovation Solution

A memory system design that includes a first transistor for supplying a write current, a second transistor in parallel, and a current copy circuit to control the second transistor based on a copied current, ensuring stable current supply to memory cells during write operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single transistor is used to supply write current to memory cells, then the circuit structure is simple, but the current supply stability is insufficient

Engineering Contradiction:
Improvecurrent supply stabilityVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent uses a current copy circuit to replicate the current flowing through the first transistor (which supplies write current to selected memory cells) and applies this copied current to control the second transistor. This copying mechanism ensures that the second transistor receives precisely the same control signal as the first transistor, enabling synchronized operation and stable current supply to both selected and unselected memory cells during write operations.

Inventive Principle:
Principle #26Copying

2Reliability

If the second transistor is controlled directly without current copying, then the circuit is simpler, but the write operation reliability deteriorates due to unstable current supply

Engineering Contradiction:
Improvewrite operation reliabilityVSAvoidcontrol circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The current copy circuit functions as a feedback mechanism by continuously monitoring the current flowing through the first transistor and using this information to control the second transistor. This feedback loop ensures that the second transistor's operation is synchronized with the first transistor, maintaining stable current supply conditions for reliable write operations across all memory cells.

Inventive Principle:
Principle #23Feedback

3Reliability

If current is not copied and controlled, then the circuit operation is faster, but the current supply to memory cells becomes unstable

Engineering Contradiction:
Improvecurrent supply stabilityVSAvoidoperation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The current copy circuit replicates the control current in real-time during write operations, allowing the second transistor to be controlled simultaneously with the first transistor without introducing significant time delays. This copying approach maintains current supply stability while minimizing operation time loss, as the copied current faithfully represents the original control signal.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS12580013B2Memory system including current copy circuit configured to copy current
Publication Date: 2026.03.17 KIOXIA CORP
  • US12580013B2 patent drawing
  • US12580013B2 patent drawing
  • US12580013B2 patent drawing

AI summary

A memory system includes a first wiring, a second wiring, a memory cell between the first and second wirings, a first power supply line configured to supply a first voltage, a first transistor between the first power supply line and the first wiring, and configured to supply a current necessary to perform a write operation to the memory cell, a second transistor arranged between the first power supply line and the first wiring, and connected in parallel with the first transistor, a second power supply line configured to supply a second voltage to the second wiring corresponding to the memory cell unselected in the write operation, and a first current copy circuit configured to copy a current flowing to the second power supply line from the second wiring corresponding to the memory cell unselected in the write operation, and configured to control the second transistor based on a copied current.