Master Chip Voltage Tuning for 3D Semiconductor Skew
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Solution Overview
Problem
In 3D semiconductor systems, processing skews among stacked slave chips lead to substantial errors in signal transmission times, degrading operation performance due to inconsistent manufacturing conditions.
Innovation Solution
A semiconductor system where a master chip controls internal voltage levels of slave chips by detecting signal phases and generating internal voltage control signals to synchronize voltage levels across all slave chips, using tuning blocks and a tuning control block to adjust voltage levels based on output signals from each chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple slave chips are stacked in 3D semiconductor system, then capacity and degree of integration are increased, but processing skews cause substantial errors in signal transmission times
Solution Approach 1:
The patent changes the voltage level parameter of slave chips dynamically. The master chip detects signal phases from each slave chip and generates internal voltage control signals to adjust the voltage levels of slave chips, thereby compensating for processing skews and synchronizing signal transmission times across all stacked chips.
2Ease of manufacture
If slave chips are manufactured under different processing conditions, then manufacturing flexibility is improved, but processing skews and operational errors increase
Solution Approach 1:
The patent implements a feedback mechanism where the master chip detects signal phases outputted from each slave chip and generates internal voltage control signals based on these detections. This feedback loop allows the system to automatically compensate for processing skews caused by varying manufacturing conditions, thereby maintaining reliable operation performance.
3Ease of operation
If voltage levels of slave chips are not synchronized, then individual chip operation is simple, but system-wide signal transmission errors occur
Solution Approach 1:
The patent segments the voltage control function: each slave chip has its voltage level independently controlled through dedicated internal voltage control signals from the master chip. This segmentation allows individual chips to maintain simple operation while the master chip coordinates their voltage levels to synchronize signal transmission times across the entire system.
Data Source
AI summary
A semiconductor system includes a master chip and a plurality of slave chips. The master chip controls internal voltage levels of the respective slave chips based on signals outputted from the plurality of slave chips such that, by referring to any one slave chip of the plurality of slave chips, internal voltage levels of remaining slave chips are controlled.