Auto-Refreshing Memory Cells in Open Bit Line Semiconductor Devices
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Solution Overview
Problem
Semiconductor memory devices with open bit line architecture face higher refreshing voltage and larger chip area costs due to the selection of multiple word lines in specific cycles, leading to increased costs and power consumption.
Innovation Solution
A method for auto-refreshing memory cells in semiconductor memory devices with an open bit line architecture, where two word lines from each memory bank's particular sectors and (M-1) word lines from other memory banks are selected in each cycle, reducing the number of selected word lines and thus lowering the refreshing voltage and chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple word lines are selected in specific cycles in open bit line architecture, then memory cells can be refreshed, but the refreshing voltage generated by the charge pump increases and the chip area becomes larger
Solution Approach 1:
The patent divides the memory banks into groups and segments the refresh operation so that not all word lines are selected simultaneously in each cycle. Instead, word lines are refreshed in distributed batches across multiple cycles, reducing the peak voltage requirement and allowing for a smaller charge pump design.
Solution Approach 2:
The patent implements periodic refresh cycles where different sets of word lines are selected in different cycles. This periodic action distributes the refresh load over time, preventing the need to generate high voltage simultaneously for all word lines, thus reducing the charge pump size and chip area.
2Reliability
If multiple word lines are selected in specific cycles in open bit line architecture, then memory cells can be refreshed, but the refreshing voltage generated by the charge pump increases
Solution Approach 1:
The refresh operation is segmented into multiple smaller operations across different cycles. By dividing the set of word lines to be refreshed into smaller groups that are processed sequentially, the voltage requirement in each cycle is reduced, leading to lower power consumption in the charge pump.
Solution Approach 2:
The patent performs partial refresh actions in each cycle rather than refreshing all word lines simultaneously. This partial action approach reduces the instantaneous voltage demand, thereby reducing the power consumption of the charge pump while still achieving complete refresh over multiple cycles.
3Reliability
If eight word lines are selected in one cycle in open bit line architecture, then memory cells are refreshed, but the chip area and cost increase compared to folded bit line architecture
Solution Approach 1:
The patent segments the word line selection into smaller groups across multiple cycles, avoiding the need to select and refresh eight word lines simultaneously. This segmentation reduces the complexity of the charge pump by lowering its voltage requirement.
Solution Approach 2:
The patent employs dynamic word line selection strategies where the set of selected word lines changes from cycle to cycle. This dynamic approach allows the system to adapt the refresh pattern to minimize peak voltage requirements, thereby reducing charge pump complexity.
Data Source
AI summary
An exemplary embodiment of the present disclosure illustrates a method for auto-refreshing memory cells in a semiconductor memory device with an open bit line architecture, wherein the semiconductor memory device comprises M memory banks, and each of the M memory banks has two particular sectors with a same index and L remained sectors with different indices. Two word lines of the two particular sectors with the same index in the memory bank and (M−1) word lines of the L remained sectors respectively in the other (M−1) memory banks are selected in one cycle. Then, memory cells of the selected word lines are refreshed.