Memory Read Circuit Pre-Charge for Bitline Coupling Control
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Solution Overview
Problem
Conventional non-volatile memory configurations suffer from parasitic coupling between bitlines, leading to reduced read window and increased risk of read errors, particularly in all bitline architectures where multiple bitlines are read simultaneously.
Innovation Solution
Implementing a power modification circuit with controlled voltage slew rates and phase delays to mitigate parasitic coupling effects, using a dual-sided sense amplifier configuration and power modification switches to stabilize bitline voltages during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple bitlines are read simultaneously in all bitline architectures, then productivity is improved, but parasitic coupling between bitlines increases causing read errors
Solution Approach 1:
The patent applies preliminary action by pre-charging bitlines to a specific voltage level before the read operation begins. This pre-charge preparation ensures that when multiple bitlines are read simultaneously, the parasitic coupling effects are minimized because the bitlines are already at the correct voltage potential, preventing voltage spikes that would cause read errors while maintaining high productivity
2Device complexity
If conventional sense amplifier configuration is used, then device complexity is reduced, but read accuracy deteriorates due to parasitic voltage interference
Solution Approach 1:
The patent introduces an intermediary element - a specifically configured sense amplifier with pre-charge transistors and controlled voltage switching - that acts as a mediator between the memory cell and the read operation. This intermediary structure isolates the parasitic coupling effects from the sensing operation, maintaining read accuracy without significantly increasing overall device complexity
Data Source
AI summary
Disclosed herein is memory device, comprising a set of memory cells provided in a plateline connected configuration; a cell operation circuit coupled to a memory cell of the set via a bitline, wherein the cell operation circuit is configured, in a read operation mode, to read from the memory cell based on an operation voltage level; a control circuit configured to control a power supply voltage supplied to the cell operation circuit in accordance with a powering sequence when initiating the read operation mode, wherein the powering sequence comprises: a first phase, in which the power supply voltage is increased to a pre-charge voltage level being lower than the operation voltage level, and a second phase, in which the power supply voltage is increased to the operation voltage level.