SRAM Array Well Strap Cells for Latch-Up Immunity

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Solution Overview

Problem

Static Random Access Memory (SRAM) arrays face challenges in achieving uniform performance across inner and dummy cells, leading to variations in charge distribution and latch-up immunity, which affects the overall reliability and efficiency of the memory array.

Innovation Solution

The implementation of well strap cells and dummy cells arranged strategically around the SRAM cell array, with specific configurations of N-well and P-well strap structures and active regions, helps in uniform charge distribution and improved latch-up immunity by reducing well inter-diffusion counter-dope effects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If well strap cells and dummy cells are strategically arranged around the SRAM cell array, then uniform charge distribution and latch-up immunity are improved, but device complexity increases

Engineering Contradiction:
Improvelatch-up immunityVSAvoidarray structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The SRAM array is divided into inner cells and dummy cells arranged in a specific pattern. The dummy cells are segmented and positioned at strategic locations around the array to control charge distribution and improve latch-up immunity without requiring complete restructuring of the entire array.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the SRAM array are given different properties: inner cells use standard configuration while dummy cells use modified configurations with specific N-well and P-well strap structures. This local differentiation addresses performance variations in specific regions without affecting the entire array design.

Inventive Principle:
Principle #3Local quality

2Reliability

If well strap cells and dummy cells are strategically arranged around the SRAM cell array, then uniform charge distribution is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvecharge distribution uniformityVSAvoidfabrication process
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The N-well and P-well strap structures are pre-configured during the fabrication process in specific patterns. The dummy cells are designed with predetermined well strap configurations that are formed during standard manufacturing steps, allowing charge distribution control to be built into the structure before operation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention modifies specific parameters of the well strap structures in dummy cells compared to inner cells, such as the positioning and dimensions of N-well and P-well regions. These parameter changes are designed to be compatible with existing fabrication processes while achieving improved charge distribution uniformity.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If dummy cells with specific N-well and P-well strap structures are used, then latch-up immunity is improved, but area occupancy increases

Engineering Contradiction:
Improvelatch-up immunityVSAvoidarray area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

Instead of modifying the entire SRAM array, only specific dummy cells at strategic locations are enhanced with additional N-well and P-well strap structures. This partial application of the improvement technique provides sufficient latch-up immunity enhancement without requiring excessive area occupancy throughout the entire array.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS11710522B2SRAM array
Publication Date: 2023.07.25 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11710522B2 patent drawing
  • US11710522B2 patent drawing
  • US11710522B2 patent drawing

AI summary

SRAM arrays are provided. A SRAM array includes a plurality of SRAM cells and a plurality of well strap cells. Each of the SRAM cells arranged in the same column of the cell array includes a first transistor formed in a first P-type well region of a substrate, a second transistor formed in an N-type well region of the substrate, and a third transistor formed in a second P-type well region of the substrate. Each well strap cell is arranged on one of the columns in the cell array and includes a first P-well strap structure formed on the first P-type well region, a second P-well strap structure formed on the second P-type well region, and an N-well strap structure formed on the N-type well region. The first and second P-well strap structures and the N-well strap structure are separated from the SRAM cells by a dummy area.