Small Swing Driver for 3D Memory Current Reduction
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Solution Overview
Problem
Current 3D memory devices, such as High Bandwidth Memory (HBM), face challenges in reducing current consumption during data transfer operations due to long-distance wiring and associated driver and receiver circuits.
Innovation Solution
The implementation of small swing drivers and repeaters using step-down power supply voltages (VPERBS and VNWBS) to reduce current consumption, along with the use of Low Vt transistors and controlled gate and back bias voltages to minimize leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If long-distance wiring is used for data transfer in 3D memory devices, then data transfer capability is improved, but current consumption increases
Solution Approach 1:
The patent changes the voltage swing parameter from large swing to small swing (e.g., from full supply voltage range to a reduced range around a mid-level voltage). This parameter change allows data to be transmitted over long distances with smaller voltage transitions, reducing the energy consumed by drivers and receivers while maintaining signal integrity through controlled impedance routing and repeater circuits.
Solution Approach 2:
The patent introduces repeater circuits as intermediary elements along the long-distance data transfer path. These repeaters receive small swing signals from upstream, restore and retransmit them with controlled voltage levels, enabling the signal to propagate across multiple die boundaries without requiring large voltage swings at each stage, thus reducing overall current consumption.
2Reliability
If level shifter circuits and amplifier circuits are used for small swing data transfer, then data transfer reliability is improved, but current consumption increases
Solution Approach 1:
The patent optimizes the operating parameters of level shifters and amplifiers by setting their supply voltages and reference levels to minimize power consumption. Instead of using full-rail voltage swings, the circuits operate with reduced voltage ranges and optimized bias points, achieving reliable data transfer while consuming less current than conventional designs.
Solution Approach 2:
The patent applies partial action by using small swing data transfer only where necessary (across TSV boundaries and long interconnects) rather than throughout the entire memory system. Local data transfers within banks or columns can use simpler, lower-power mechanisms, while small swing with level shifters is applied selectively to long-distance paths, optimizing the trade-off between reliability and power consumption.
3Area of stationary object
If 3D memory structure is implemented, then chip size is reduced, but wiring complexity and current consumption increase
Solution Approach 1:
The patent transitions data transfer from a two-dimensional planar routing to a three-dimensional vertical routing through TSVs. By stacking memory banks vertically and using TSVs for inter-layer communication, the physical footprint is reduced while the wiring paths become more complex. Small swing data transfer is applied to these vertical interconnects to manage the increased current consumption from multiple stacking layers and long-distance horizontal routing within layers.
Data Source
AI summary
Embodiments of the disclosure provide an apparatus comprising a small swing driver and a small swing repeater on data transfer wiring of a memory device. The small swing driver includes 1st pair of 1st-type p/n-MOS transistors and 2nd pair of 2nd-type p/n-MOS transistors. The small swing repeater includes 3rd pair of 1st-type p/n-MOS transistors and 4th pair of 2nd-type p/n-MOS transistors. In the small swing driver, positive power supply voltage and 1st step-down power supply voltage are applied to gate and source of 2nd-type p-MOS transistor of 2nd pair, and 2nd step-down power supply voltage is applied to 2nd-type p-MOS transistor of 2nd pair as backbias voltage. In the small swing repeater, 1st and 2nd step-down power supply voltages are applied to source and gate of 2nd-type p-MOS transistor of 4th pair. 2nd step-down power supply voltage is also applied to 2nd-type p-MOS transistor of 4th pair as backbias voltage.