Vertical FeFET Structure for Higher Density and Lower Interference
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Solution Overview
Problem
Existing ferroelectric field effect transistors (FeFETs) are limited by their horizontal structure, which restricts integration density and scalability in logic devices and memory devices, as well as the variability of threshold voltage due to polarization direction and intensity.
Innovation Solution
A vertical structure is introduced for FeFETs, featuring a gate electrode, ferroelectric layer, and channel layer stacked in a vertical direction, with source/drain contacts and gate contacts arranged to minimize electrical interference, allowing for a hexagonal lattice arrangement of transistors and increased integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a horizontal structure is used for ferroelectric field effect transistors, then the device can be manufactured with conventional processes, but the integration density and scalability are restricted
Solution Approach 1:
The patent transitions from a planar horizontal structure to a vertical three-dimensional structure for the ferroelectric field effect transistor. The gate electrode, ferroelectric layer, and channel layer are stacked vertically, with source and drain regions positioned at different heights, enabling space-efficient packing and higher integration density while maintaining compatibility with conventional semiconductor manufacturing processes
2Quantity of substance
If the transistor area is reduced to increase integration density, then more transistors can be packed in the same area, but electrical interference between adjacent transistors increases
Solution Approach 1:
By stacking the transistor components vertically, the patent separates adjacent transistors in the vertical dimension, reducing electrical interference while maintaining high integration density. The vertical arrangement allows better isolation between source and drain regions of neighboring transistors compared to planar layouts
Solution Approach 2:
The patent employs a nested structure where the gate electrode is surrounded by the ferroelectric layer, which is in turn surrounded by the channel layer and source/drain regions. This concentric arrangement minimizes the horizontal footprint while maintaining adequate electrical isolation, allowing higher density without increasing interference
3Quantity of substance
If a vertical structure is adopted, then integration density and scalability are enhanced, but the device complexity increases
Solution Approach 1:
The vertical stacking of gate electrode, ferroelectric layer, and channel layer creates a three-dimensional structure that achieves higher integration density. While the spatial arrangement becomes more complex, the manufacturing process remains relatively straightforward by extending conventional planar fabrication techniques into the vertical dimension through sequential deposition and patterning steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The vertical structure enhances integration density and scalability, reducing the area of each memory cell and enabling multi-layered semiconductor devices with improved performance and efficiency.
Implementation Method 1
Ferroelectrics are materials that have ferroelectricity, which maintains spontaneous polarization by aligning internal electric dipole moments even when an electric field is no longer being applied
Data Source
AI summary
Provided are a ferroelectric field effect transistor having a vertical structure, a semiconductor device including the ferroelectric field effect transistor, a method of fabricating the semiconductor device, and an operating method of the semiconductor device. A ferroelectric field effect transistor includes a gate electrode extending in the first direction, a ferroelectric layer extending in the first direction on a side surface of the gate electrode, a channel layer extending in the first direction on a side surface of the ferroelectric layer, a first source/drain contact electrically connected to a lower surface of the channel layer, a second source/drain contact electrically connected to an upper surface of the channel layer, and a gate contact electrically connected to an upper surface of the gate electrode.