CFET Memory Array Fly Word Lines for Faster Edge Access
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Solution Overview
Problem
Existing integrated circuit (IC) devices face challenges in reducing word line loading and timing delays due to increased resistance and capacitance, particularly when accessing memory cells at the edges of the memory array, which limits access speed.
Innovation Solution
Implementing a fly word line configuration using both front side and back side word lines, where one word line 'flies over' the memory cells without electrical coupling, and the other is physically shorter, reducing capacitance and resistance, thereby improving access speed and reducing word line loading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional word line configuration is used to access memory cells, then the memory array can be accessed, but timing delays and word line loading increase due to increased resistance and capacitance, limiting access speed
Solution Approach 1:
The word line configuration is segmented into two distinct types: fly word lines that extend over memory cells without electrical coupling, and short word lines that are physically shorter and reduce capacitance. This segmentation allows different portions of the memory array to be accessed through optimized paths, reducing overall timing delays and improving access speed.
2Area of stationary object
If word line length is increased to cover more memory cells, then more memory cells can be accessed, but resistance and capacitance increase, worsening timing delays
Solution Approach 1:
Fly word lines act as intermediaries that extend over memory cells without forming direct electrical connections. This allows the word line structure to cover a larger memory array area while avoiding the harmful effects of increased capacitance and resistance that would normally accompany longer word lines, thus maintaining timing performance.
3Ease of operation
If multi-layer word lines are implemented to reduce loading, then word line loading can be reduced, but manufacturing complexity increases
Solution Approach 1:
Instead of using multi-layer word line structures to reduce loading, the invention inverts the approach by using fly word lines that extend over memory cells without electrical coupling. This single-layer approach achieves reduced word line loading while avoiding the manufacturing complexity of multi-layer structures.
Data Source
AI summary
An integrated circuit (IC) device includes a memory array including a plurality of memory cells, a first word line over the memory array and electrically coupled to at least one first memory cell among the plurality of memory cells, and a second word line under the memory array and electrically coupled to at least one second memory cell among the plurality of memory cells. Each memory cell among the plurality of memory cells includes complementary field-effect transistor (CFET) devices.