DRAM Row Hammer Detection Cells and Proactive Refresh
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Solution Overview
Problem
Dynamic random access memory (DRAM) devices face data loss due to parasitic effects and row-hammer errors, where frequent memory refreshes increase power consumption and processing costs, and existing error correction techniques are ineffective for large quantities of flipped bits.
Innovation Solution
Incorporating additional detection cells in memory rows that are more susceptible to parasitic interactions, allowing for early detection of charge leakage and triggering proactive memory refreshes before data loss occurs, using a voting algorithm to minimize false positives.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If more frequent memory refreshes are performed to prevent data loss, then data integrity is improved, but power consumption increases
Solution Approach 1:
The patent implements detection bits that proactively monitor for row hammer attacks before data corruption occurs. When detection bits indicate potential attacks, the system performs targeted refreshes of affected memory rows in advance, preventing data loss without requiring continuous full-memory refreshing, thus reducing overall power consumption while maintaining data integrity
Solution Approach 2:
Instead of uniformly refreshing all memory rows, the patent applies refresh operations selectively to specific rows that are detected as being under attack or at risk. This localized approach maintains data integrity in vulnerable areas while avoiding unnecessary power consumption in unaffected regions
2Reliability
If more frequent memory refreshes are performed to prevent data loss, then data integrity is improved, but processing performance deteriorates
Solution Approach 1:
The detection bits continuously monitor for row hammer attacks in the background without interrupting normal memory operations. When attacks are detected, refreshes are triggered proactively, allowing the system to maintain high processing performance while ensuring data integrity through timely, targeted interventions rather than frequent blanket refreshes
3Measurement precision
If additional detection cells are added to memory rows, then detection accuracy is improved, but device complexity increases
Solution Approach 1:
The patent divides each memory row into functional segments: data bits for storing information and separate detection bits for monitoring attacks. This segmentation allows independent optimization of each function, improving detection accuracy without significantly increasing overall complexity since detection bits use the same simple structure as data bits
Solution Approach 2:
The patent changes the functional parameter of specific bits from data storage to attack detection. By modifying the role of certain bits rather than adding entirely new complex detection circuits, the system achieves improved detection accuracy with minimal increase in device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces data loss by initiating refreshes before data is corrupted, maintaining data integrity while minimizing power consumption and processing costs, and is applicable to various memory types susceptible to similar effects.
Implementation Method 1
the feature size of memory cells has decreased to increase the density of memory cells in a memory device. Increasing the memory cell density provides increased storage capacity in the memory device. However, this increased density can also lead to loss of data due to, for example, parasitic effects.
Implementation Method 2
Capacitor-based memory cells of a dynamic random access memory (DRAM) device store data by storing charges that represent the corresponding stored data. These physically smaller cells are limited to storing correspondingly smaller charges. This results in a lower noise margin and a higher potential for parasitic interaction between cells or between cells and other parts of the DRAM circuit. This interaction, manifested as a charge leakage from one cell to nearby cells in adjacent rows or from other DRAM circuits to adjacent cells, can result in unintended changing of the memory contents of these nearby cells.
Implementation Method 3
Capacitor-based memory cells of a dynamic random access memory (DRAM) device store data by storing charges that represent the corresponding stored data.
Data Source
AI summary
Systems and methods for detecting a row hammer in a memory comprising a plurality of memory cells arranged in a plurality of rows may include: a plurality of detection cells in a subject row of memory cells, the detection cells to be set to respective initial states and configured to transition to a state different from their initial states in response to activations of memory cells in an adjacent row of memory cells; a comparison circuit to compare current states of the detection cells with initial states of the detection cells and to determine whether any of the detection cells have a current state that is different from their corresponding initial states; and a trigger circuit to trigger a refresh of the memory cells in the subject row based on a detection of detection cells in the subject row having current states that are different from their corresponding initial states.