Word Line Driver Test Timing for Memory Defect Detection
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in detecting defects in word line drivers, which can impact the performance of read and write operations.
Innovation Solution
A semiconductor device is designed with a test control circuit and word line control circuit to generate specific signals for activating and deactivating word line drivers in a test mode, allowing for the detection of defects by delaying signal input timing and monitoring voltage levels during precharge operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a test mode is implemented to detect defects in word line drivers, then the reliability of read and write operations is improved, but the device complexity increases due to additional test control circuits and signal generation mechanisms
Solution Approach 1:
The test control circuit is designed to perform multiple functions: it generates test patterns, controls test signal timing, and detects defects in word line drivers. By making the test control circuit multi-functional, the patent reduces the need for separate dedicated circuits for each test function, thereby improving reliability while limiting the increase in device complexity.
Solution Approach 2:
The test mode utilizes existing circuit structures and signal paths within the semiconductor device to perform self-diagnosis of word line driver defects. The device uses its own internal resources (existing word lines, drivers, and signal routing) to conduct tests, rather than requiring entirely external test equipment, thus improving reliability while minimizing additional complexity.
2Measurement precision
If signal timing is delayed to enable defect detection during precharge operations, then the measurement precision of word line driver defects is improved, but the productivity of memory operations decreases due to extended test cycles
Solution Approach 1:
The test mode implements periodic timing delays in signal generation during precharge operations, allowing the system to observe word line driver behavior at critical moments. By applying periodic delays rather than continuous monitoring, the patent achieves high measurement precision for defect detection while minimizing the overall impact on operational productivity.
Solution Approach 2:
The test control circuit generates test signals and applies timing delays in advance during the precharge phase, before actual read or write operations begin. This preliminary testing allows defect detection without interfering with the timing-critical data operations, thereby maintaining productivity while achieving high measurement precision.
3Reliability
If multiple voltage driving signals and discharge signals are generated to control word line drivers, then the reliability of defect detection is improved, but the device complexity increases due to additional signal generation circuits
Solution Approach 1:
The patent combines multiple voltage driving signal generation functions and discharge signal generation functions into integrated control circuits. By merging these functions, the system achieves reliable defect detection through comprehensive signal control while reducing the overall device complexity compared to having separate dedicated circuits for each signal type.
Solution Approach 2:
The voltage driving signal generation circuit and discharge signal generation circuit are designed as multi-functional units that can generate different signal types and control multiple word line drivers. This universality allows reliable defect detection across all drivers while minimizing the number of separate circuits needed, thus limiting the increase in device complexity.
Data Source
AI summary
A semiconductor device includes a test control circuit configured to enter a test mode and configured to generate a test word line precharge signal, based on a test mode entry signal, an active pulse, a precharge pulse, a reset signal, and a test code; a mat including a plurality of word line drivers; and a word line control circuit configured to generate a word line driving signal, a plurality of voltage driving signals, and a plurality of voltage discharge signals for controlling operations of the plurality of word line drivers, based on the test word line precharge signal, a mat enable signal, and a plurality of internal addresses. The word line driving signal is a signal that is enabled after a start of an active operation and that is disabled after a set period from timing for a precharge operation.