DRAM Bit Line Staircase Structure for Connection Reliability

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Solution Overview

Problem

The common bit line in dynamic random access memory (DRAM) is prone to disconnection during manufacturing, leading to poor memory performance.

Innovation Solution

The DRAM design includes bit line functional groups with a first bit line structure surrounding a first isolation layer, multiple second bit line structures coupled through selection transistors, and a staircase structure on one side of the first bit line, featuring conductive stairs to ensure connection integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a common bit line is used in DRAM manufacturing, then storage density is improved, but the bit line is prone to disconnection and manufacturing reliability deteriorates

Engineering Contradiction:
Improvestorage densityVSAvoidbit line connection reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The bit line is divided into multiple segments: first bit line portions extending in a first direction, second bit line portions extending in a second direction perpendicular to the first, and third bit line portions extending in the first direction. These segments are arranged in an interlaced pattern to form a grid-like structure that reduces stress concentration and prevents complete disconnection if one segment fails.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The bit line structure embeds multiple functional layers within a three-dimensional configuration. Conductive plugs are positioned at intersections, with conductive barriers surrounding them, and the bit line portions are nested around these central conductive elements, creating a robust interconnected structure where failure of one element does not compromise the entire bit line.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Manufacturing precision

If bit line structure complexity is increased to prevent disconnection, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:
Improvebit line connection precisionVSAvoidbit line structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The conductive plugs serve multiple functions: they act as connection points between bit line portions, serve as structural anchors for the conductive barriers, and function as stress distribution elements. The conductive barriers simultaneously provide electrical isolation and mechanical support. This multi-functionality reduces the need for additional separate components, maintaining manufacturing precision without proportionally increasing device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The invention merges the electrical connection function, electrical isolation function, and mechanical support function into a single integrated three-dimensional structure. The conductive plugs and barriers are formed together in the same manufacturing sequence, and the bit line portions are continuously connected through these merged elements, reducing the number of separate manufacturing steps and components while achieving high connection precision.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20260075796A1Memory and manufacturing method therefor, and electronic device
Publication Date: 2026.03.12 RUILI INTEGRATED CIRCUIT CO LTD
  • US20260075796A1 patent drawing
  • US20260075796A1 patent drawing
  • US20260075796A1 patent drawing

AI summary

The present disclosure provides a memory and a manufacturing method therefor, and an electronic device. The memory includes multiple bit line functional groups, multiple storage units, and a staircase structure, and each of the bit line functional groups includes a first bit line structure, multiple second bit line structures, and multiple selection transistors. The first bit line structure includes a first isolation layer and a first bit line circumferentially surrounding the first isolation layer. Multiple second bit line structures are provided on a first side of the first bit line in a third direction, a staircase structure is provided on a second side of the first bit line in the third direction, and multiple conductive stairs of the staircase structure are respectively coupled to corresponding first bit lines.