Main Word Line Driver for 3D Memory Stacking
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Solution Overview
Problem
Conventional two-dimensional memory apparatus designs have reached their limit in increasing data storage capacity, necessitating the development of three-dimensional memory apparatuses that can efficiently stack memory cell arrays to maximize data storage within a given area while maintaining effective data communication and processing speeds.
Innovation Solution
The implementation of a main word line driver with an enable control signal generation circuit, first and second drivers, and a memory apparatus comprising multiple memory cell arrays, sub-word line driver blocks, and a main word line driver block that utilize pre-decoding signals and selection signals to enable main word line signals, reducing the number of wires and enhancing power distribution by selectively activating word lines across stacked memory cell arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional memory design is used to increase data storage capacity, then manufacturing complexity is reduced, but data storage capacity reaches its limit
Solution Approach 1:
The patent transitions from two-dimensional memory cell array arrangement to three-dimensional stacked architecture, where multiple memory cell arrays are vertically stacked and controlled by main word line signals. This dimensional change enables significantly increased data storage capacity within the same footprint area, overcoming the limitations of planar scaling.
2Quantity of substance
If three-dimensional stacked memory cell arrays are implemented to increase data storage capacity, then data storage capacity increases, but wire load and power distribution complexity increase
Solution Approach 1:
The patent divides the control of stacked memory cell arrays into segments: main word line drivers generate control signals, which are then distributed to multiple sub-word line driver blocks. Each sub-word line driver block independently controls specific word lines within its associated memory cell array, reducing the complexity of direct full-system wiring.
Solution Approach 2:
Sub-word line driver blocks serve as intermediary components between the main word line drivers and the memory cell arrays. These intermediaries receive enable signals from main word line drivers and selectively activate specific word lines, thereby reducing the direct wire load on main word line signals while maintaining control over stacked arrays.
3Quantity of substance
If more memory cell arrays are stacked to increase data storage capacity, then data storage capacity increases, but driving power for main word line signals decreases
Solution Approach 1:
The patent segments the word line control function across multiple sub-word line driver blocks distributed throughout the stacked structure. Each sub-driver is positioned close to its associated memory cell array, reducing signal transmission distance and power loss, thereby maintaining adequate driving power even as the number of stacked arrays increases.
Solution Approach 2:
Sub-word line driver blocks act as power-efficient intermediaries that receive low-power enable signals from main word line drivers and generate the actual high-current word line activation signals locally. This intermediary approach reduces the power burden on main word line signals while enabling control of numerous stacked memory cell arrays.
Data Source
AI summary
A memory apparatus includes a first main word line signal, a second main word line signal, and a word line driver. The first main word line signal is coupled to a first sub-word line driver block including n sub-word line drivers. The second main word line signal is coupled to a second sub-word line driver block including n sub-word line drivers. The main word line driver is configured to selectively enable one of the first and second main word line signals.