SRAM Read Stability via Capacitive Voltage Boost
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Solution Overview
Problem
Static noise margin (SNM) of SRAM circuits deteriorates at low supply voltage modes, leading to reduced read stability and timing penalties due to existing read assist techniques.
Innovation Solution
A memory circuit design that includes a word line and a high supply line capacitively coupled to boost the cell supply voltage, allowing for a voltage boost of up to 10% above the high supply voltage, and a word line under-voltage circuit that delays under-voltage application to maintain full voltage during initial read operations, thereby enhancing SNM and read stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read assist circuits are connected to the SRAM to increase stability in low supply voltage mode, then static noise margin is improved, but timing penalty occurs due to reduced read current
Solution Approach 1:
The patent applies preliminary action by pre-charging the bit lines to a higher voltage level (e.g., 0.7V) before the read operation begins. This preliminary voltage setup ensures that when the read operation occurs, the voltage differential is already optimized for detection, eliminating the need for timing delays while maintaining improved static noise margin through the voltage boost mechanism
2Reliability
If word line under-drive technique is used to improve static noise margin by reducing pass gate transistor strength, then stability is enhanced, but read current is reduced causing timing penalty
Solution Approach 1:
The patent applies local quality by selectively applying different voltage levels to different parts of the circuit: the bit lines are boosted to a higher voltage (e.g., 0.7V) while the word line operates at its normal voltage level. This localized voltage enhancement improves the signal differential for detection without affecting the overall read current through the pass gate transistors, thus avoiding timing penalties while maintaining stability enhancement
3Use of energy by moving object
If supply voltage is reduced to low voltage mode for energy efficiency, then power consumption is reduced, but static noise margin deteriorates significantly
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the bit line voltage parameter during read operations. The bit lines are charged to a higher voltage level (e.g., 0.7V instead of the standard 0.6V) while the supply voltage remains at the low level (0.6V). This parameter modification creates a larger voltage differential for sense amplifier detection, effectively improving static noise margin without increasing the overall power consumption of the memory cell
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves SRAM read stability and speed by increasing the strength of pull-down transistors, switching threshold, and reducing pass transistor strength, while avoiding write margin degradation and timing penalties.
Implementation Method 1
the first and second metal lines extend immediately adjacent to each other in a same metallization level so that a capacitance is formed between the first and second metal lines
Data Source
AI summary
Read stability of a memory is enhanced in low voltage operation mode by selectively boosting a cell supply voltage for a row of memory cells. The boosted voltage results from a capacitive coupling to the word line in that row. The capacitive coupling is implemented by running the metal line of the power supply line for the cell supply voltage and the metal line for the word line adjacent to each other in a common metallization level. The selective voltage boost is controlled in response to operation of a modified memory cell exhibiting a deteriorated write margin. An output of the modified memory cell is compared to a threshold to generate a signal for controlling the selective voltage boost. Word line under-voltage circuitry is further provided to control application of an under-voltage to the word line.