Memory Sensing Timing to Prevent Plate-Digit Line Voltage Disturb
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Solution Overview
Problem
Voltage offset between the plate and digit line in memory cells causes voltage disturb, affecting performance and reliability, particularly in ferroelectric RAM (FeRAM) devices.
Innovation Solution
Control the slew rate of the plate voltage by delaying its application relative to the digit line voltage during sensing to mitigate voltage offset, and/or apply the digit line voltage faster than the plate voltage, using circuitry with drivers and delay components to manage the voltage ramping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If voltage is applied simultaneously to the plate and digit line during sensing, then sensing speed is improved, but voltage offset causes voltage disturb on unselected digit lines
Solution Approach 1:
The patent applies voltage to the digit line before applying voltage to the plate during sensing operations. This preliminary action on the digit line establishes a reference voltage level that compensates for the voltage offset that would otherwise cause disturb on unselected digit lines, thereby maintaining fast sensing speed while eliminating the harmful voltage disturb
Solution Approach 2:
The patent changes the timing parameter of voltage application by introducing a delay between when voltage is applied to the digit line versus when it is applied to the plate. This parameter change in voltage application timing allows the system to maintain high sensing speed while preventing voltage offset-induced disturb on unselected lines
2Object-affected harmful factors
If voltage ramping is controlled to prevent voltage offset, then voltage disturb is reduced, but sensing operation complexity increases
Solution Approach 1:
The patent uses preliminary voltage application to the digit line with controlled ramping to establish a reference level before plate voltage is applied. This preliminary action with controlled voltage ramping prevents voltage offset issues while maintaining relatively simple sensing operations through straightforward voltage sequencing
Solution Approach 2:
The patent introduces the digit line voltage as an intermediary element that mediates between the plate voltage and the unselected digit lines. By controlling the digit line voltage ramping rate, it acts as a buffer that prevents voltage offset from causing disturb on unselected lines without requiring complex sensing circuitry
Data Source
AI summary
The present disclosure includes apparatuses, methods, and systems for compensating for voltage offset in memory. An embodiment includes a memory having an array of memory cells, and circuitry configured to sense a data state of a memory cell of the array by applying a voltage to a data line coupled to the memory cell and a plate of the memory cell, wherein the voltage applied to the plate is delayed relative to the voltage applied to the data line.