2T1C Erasable Non-Volatile Memory Cell with Merged Doped Regions
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Solution Overview
Problem
Conventional erasable programmable non-volatile memory cells are large in size due to design rules of medium voltage devices and extended floating gates, necessitating high operation voltages and slower speeds.
Innovation Solution
The memory cell design incorporates a select transistor and a floating gate transistor with separate manufacturing processes for medium and low voltage devices, reducing size and voltage requirements by using merged doped regions and a metal layer to form a 2T1C structure with a plate capacitor, allowing for reduced program and erase voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If medium voltage device design rules are used, then high operation voltages can be achieved, but device size increases and speed decreases
Solution Approach 1:
The patent divides the memory cell into two separate transistors: a medium voltage select transistor for high voltage operations and a low voltage floating gate transistor for fast data storage operations. This segmentation allows each transistor to be optimized for its specific voltage requirement, achieving both high voltage capability and fast speed without compromise.
Solution Approach 2:
The shared doped region serves multiple functions: it acts as the source for the select transistor, the drain for the floating gate transistor, and provides electrical connection to both transistors. This multi-functionality reduces the total number of doped regions needed, thereby reducing device size while maintaining both high voltage and fast operation capabilities.
2Adaptability or versatility
If extended floating gate is used, then erase functionality is achieved, but device size increases
Solution Approach 1:
The patent extracts the erase gate functionality from the floating gate structure itself and implements it as a separate medium voltage select transistor with its own gate. This allows the floating gate to be smaller and not require external extension, while still achieving erase functionality through the select transistor's control.
Solution Approach 2:
The patent merges the source of the select transistor and the drain of the floating gate transistor into a single shared doped region. This merging reduces the total area required for the memory cell while maintaining both program and erase functionalities through coordinated control of the two transistors.
3Power
If separate manufacturing processes for medium and low voltage devices are used, then voltage requirements are reduced, but device complexity increases
Solution Approach 1:
The patent applies different manufacturing process qualities to different parts of the device: medium voltage processes are used for the select transistor and low voltage processes for the floating gate transistor. This local differentiation allows each transistor to be optimized for its voltage requirement while using standard CMOS compatible processes.
Solution Approach 2:
The patent performs preliminary actions by forming the shared doped region and gate dielectric layers before differentiating the transistor structures. This preliminary fabrication creates a common foundation that simplifies subsequent separate processing steps for medium and low voltage devices, reducing overall manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The new design achieves a significant size reduction of up to 50% and lowers program and erase voltages, enhancing programming efficiency and operational speed while maintaining functionality.
Implementation Method 1
The floating gate of the floating gate transistor can store hot carriers. The storage state of the floating gate transistor can be determined according to the amount of stored hot carriers.
Implementation Method 2
a gate dielectric layer 464 is located under the select gate 454 and contacted with the surface of the N-well region NW. Similarly, a gate dielectric layer 465 is located under the floating gate 455.
Data Source
AI summary
An erasable programmable non-volatile memory cell includes a well region, a first gate structure, a second gate structure, a first merged doped region, a second merged doped region and a third merged doped region. The first merged doped region is located beside a first side of the first gate structure. The second merged doped region is arranged between a second side of the first gate structure and a first side of the second gate structure. The third merged doped region is located beside a second side of the second gate structure. The first merged doped region, the first gate structure and the second merged doped region are collaboratively formed as a select transistor. The second merged doped region, the second gate structure and the third merged doped region are collaboratively formed as a floating gate transistor.