Read-Only Memories TRIZ Cases
- Semiconductor Memory Interconnect Stacking for Higher Capacity
Stacked interconnect layers and vertical memory pillars increase capacity while addressing manufacturing complexity in 3D memory structures.
- One-Time Programmable Memory Cell With Fuse-Based Error Correction
A fuse and anti-fuse OTP cell enables direct programming-error correction while simplifying layout and reducing area.
- Dynamic Latches Above 3D Memory Arrays for Parallel Programming
Dynamic latches above a 3D non-volatile memory array add latch capacity for concurrent sub-block programming, reducing operations and latency.
- NAND Memory Read Offset Adaptation for Fewer Re-Reads
Successful re-reads identify a baseline offset for NAND memory reads, reducing repeated attempts, cell wear, time, and power.
- Schottky-Barrier Memory Cells for CMOS-Compatible Nonvolatile Storage
Paired p-type transistors use Schottky barrier junctions and trapped avalanche hot electrons to hold data nonvolatilely in CMOS-compatible memory.