Schottky-Barrier Memory Cells for CMOS-Compatible Nonvolatile Storage
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving reliable data storage with low-cost manufacturing processes compatible with CMOS technology, particularly in holding small to medium capacity data in a nonvolatile manner.
Innovation Solution
A semiconductor memory device utilizing a pair of transistors with a Schottky barrier junction on a p-type substrate, where avalanche hot electrons are trapped in an insulating film around the gate to hold data nonvolatilely, compatible with CMOS processes of several tens of nanometers, and featuring a memory cell array with bit and word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a Schottky barrier junction transistor is used for memory cell, then manufacturing cost is reduced and CMOS compatibility is achieved, but data storage reliability is insufficient
Solution Approach 1:
The memory cell is divided into two separate p-type transistors with Schottky barrier junctions instead of using a single transistor or complex structure. This segmentation allows each transistor to be independently optimized for both manufacturability and reliability, while maintaining CMOS process compatibility. The dual-transistor configuration provides redundant storage paths that improve data retention reliability.
Solution Approach 2:
The patent combines Schottky barrier junction technology with CMOS manufacturing processes, creating a hybrid structure that leverages the low-cost advantages of Schottky junctions while integrating them into the reliable CMOS framework. The composite approach uses standard CMOS materials and processes supplemented by Schottky metal contacts, achieving both cost reduction and maintained reliability.
2Duration of action of stationary object
If avalanche hot electrons are trapped in insulating film for nonvolatile storage, then data retention is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent optimizes the insulating film thickness parameter within specific ranges that balance data retention performance with manufacturing feasibility. By carefully selecting and controlling the thickness parameter of the insulating layer, the design achieves adequate charge trapping capability for nonvolatile storage while remaining compatible with standard CMOS fabrication tolerances.
3Quantity of substance
If memory cell array with bit line pair and source line is implemented, then storage capacity is increased, but device complexity increases
Solution Approach 1:
The bit line pair and source line configuration is designed to serve multiple functions simultaneously: data writing, data reading, and data verification. The same physical structures are reused across different operational modes, increasing storage capacity and functionality without proportionally increasing device complexity. The universal line structure reduces the number of dedicated components needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides improved reliability and cost-effectiveness while enabling storage of several bits to several megabits of data nonvolatilely, maintaining compatibility with CMOS manufacturing processes.
Implementation Method 1
one of terminals of the transistor is a Schottky barrier junction consisting of a metal thin film formed on the n-type well
Implementation Method 2
avalanche hot electrons are trapped in an insulating film around a gate of the transistor, thereby holding data in a Nonvolatile manner
Data Source
AI summary
A semiconductor memory device includes a bit line pairs, a source line, a word line, and a memory cell array including a plurality of memory cells arranged in a row and column directions, wherein the memory cell is a pair of p-type transistors formed on an n-type well, wherein one of terminals of the transistor is a Schottky barrier junction consisting of a metal thin film formed on the n-type well, and the other terminal is connected to the source line.