Semiconductor Memory Interconnect Stacking for Higher Capacity
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving high integration and capacity while maintaining efficient data storage and retrieval operations, particularly in three-dimensional memory structures.
Innovation Solution
A semiconductor memory device with a specific configuration that includes a semiconductor layer, multiple interconnect layers, memory pillars, and members that enhance electrical connectivity and structural integrity, allowing for efficient data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional memory structure is adopted for higher integration, then storage capacity increases, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The patent transitions from planar two-dimensional memory structures to three-dimensional vertical structures by stacking multiple interconnect layers (first interconnect layer, second interconnect layer) above the substrate, with memory pillars extending vertically to contact the semiconductor layer. This dimensional change enables higher storage capacity within the same footprint area.
Solution Approach 2:
The memory device is segmented into distinct functional layers including substrate, first interconnect layer, second interconnect layer, semiconductor layer, and memory pillars. This segmentation allows independent optimization and manufacturing of each layer, reducing overall process difficulty while maintaining high integration.
2Reliability
If multiple interconnect layers are stacked to increase integration, then electrical connectivity improves, but structural integrity and alignment precision become more difficult to maintain
Solution Approach 1:
The first and second interconnect layers are merged in the vertical stacking sequence, with both layers positioned between the substrate and semiconductor layer. This merging creates a consolidated interconnect structure that maintains electrical connectivity while simplifying the overall manufacturing process by reducing the number of separate stacking operations required.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes: a semiconductor layer arranged above a substrate in a first direction; a first interconnect layer between the substrate and the semiconductor layer; a second interconnect layer arranged adjacent to the first interconnect layer in a second direction; a plurality of memory pillars; and a first member between the first interconnect layer and the second interconnect layer. The semiconductor layer has, on a side of a second surface facing a first surface in contact with the first member, a first projecting portion projecting in the first direction and overlapping a part of an area in the first direction, the area being provided with the first interconnect layer and the first member.