Dynamic Latches Above 3D Memory Arrays for Parallel Programming
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Solution Overview
Problem
Existing memory devices face challenges in efficiently programming multiple sub-blocks due to limited space for latches under the memory array, leading to increased latency and reduced performance, particularly in high-density non-volatile memory devices like TLCs.
Innovation Solution
Implementing dynamic latches above the 3D non-volatile memory array, with a fixed number of latches under the array and additional latches positioned above, allowing concurrent programming of multiple sub-blocks using a single programming pulse without increasing the device's footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If latches are placed only under the memory array, then device footprint is minimized, but programming performance and parallelism are limited
Solution Approach 1:
The patent places latches in two different spatial dimensions: under the memory array (first logic layer) and above the memory array (second logic layer). This three-dimensional arrangement enables concurrent programming of multiple sub-blocks by providing additional latch resources without increasing the lateral footprint of the device, thereby improving programming performance and parallelism.
2Productivity
If more latches are added to support concurrent programming, then programming parallelism improves, but device area increases
Solution Approach 1:
By utilizing the vertical dimension above the memory array in addition to the space under the array, the patent accommodates more latches without increasing lateral device footprint. This enables concurrent programming of multiple sub-blocks while maintaining a compact device form factor.
3Loss of time
If a fixed number of latches are used under the array, then device complexity is reduced, but programming latency increases
Solution Approach 1:
The patent reduces programming latency by placing additional latches above the memory array, enabling concurrent programming operations. While this increases device complexity, the patent manages this through systematic organization of latches in two logic layers with controlled interconnections, achieving a balance between performance and complexity.
Solution Approach 2:
The patent divides the latch resources into two separate logic layers (under and above the memory array), allowing independent optimization and management of each layer. This segmentation enables concurrent programming of multiple sub-blocks while maintaining manageable device complexity through modular organization.
Data Source
AI summary
Control logic in a memory device causes a pass voltage to be applied to a plurality of wordlines of a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and the pass voltage to boost a channel potential of each of the plurality of sub-blocks to a boost voltage. The control logic further selectively discharges the boost voltage from one or more of the plurality of sub-blocks according to a data pattern representing a sequence of bits to be programmed to respective memory cells of the plurality of sub-blocks. In addition, the control logic causes a single programming pulse to be applied to a selected wordline of the plurality of wordlines of the block to program the respective memory cells of the plurality of sub-blocks according to the data pattern.