3D Neural Network Accelerator Tile Bypass for Yield Recovery
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Solution Overview
Problem
Three-dimensionally stacked neural network accelerators often suffer from reduced yield due to faulty computing tiles, which can render the entire accelerator inoperable if not addressed.
Innovation Solution
The solution involves modifying the dataflow configuration to bypass faulty tiles by routing outputs from tiles before the faulty one to inputs on different neural network dies, thereby ensuring continued functionality of the accelerator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If more computing tiles are stacked vertically to increase processing capacity, then the computing power and compactness are improved, but the probability of having faulty tiles increases, which can render the entire accelerator inoperable
Solution Approach 1:
The patent segments the dataflow configuration into multiple independent paths through the tile array. By dividing the computational workload across different routing paths, the system can bypass faulty tiles while maintaining overall functionality. The dataflow is segmented such that data can travel through alternative sequences of tiles rather than requiring a single linear path through all tiles.
Solution Approach 2:
The patent implements dynamic reconfiguration of dataflow paths based on detected tile functionality. The system can adaptively modify routing configurations at runtime or during initialization to避开 faulty tiles. This dynamic adjustment allows the accelerator to maintain high utilization of functional tiles while gracefully handling manufacturing defects.
2Ease of manufacture
If traditional fabrication mechanisms are used for three-dimensionally stacked accelerators, then manufacturing cost and compactness are improved, but the yield of fault-free accelerators deteriorates
Solution Approach 1:
The patent converts the harmful effect of faulty tiles into a beneficial feature by implementing tolerance to defects. Instead of requiring perfect fabrication yield, the system is designed to function correctly even with faulty tiles present. This approach transforms manufacturing imperfections from deal-breakers into manageable conditions, effectively converting the harm of low yield into the benefit of robust, defect-tolerant operation.
Solution Approach 2:
The patent changes the operational parameters of the accelerator by modifying dataflow configurations to accommodate faulty tiles. By adjusting routing parameters and computational distribution, the system maintains optimal performance despite hardware defects. This parameter adaptation allows standard fabrication processes to produce functional accelerators without requiring enhanced manufacturing precision.
3Device complexity
If faulty tiles are included in the dataflow configuration, then device complexity is reduced, but the accelerator becomes inoperable
Solution Approach 1:
The patent performs preliminary identification and characterization of faulty tiles during initialization or manufacturing testing. By detecting and marking defective tiles before normal operation begins, the system can pre-compute alternative routing paths that bypass faulty regions. This preliminary action prevents faulty tiles from disrupting operational dataflows while minimizing the complexity increase to the control logic.
Data Source
AI summary
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for three-dimensionally stacked neural network accelerators. In one aspect, a method includes obtaining data specifying that a tile from a plurality of tiles in a three-dimensionally stacked neural network accelerator is a faulty tile. The three-dimensionally stacked neural network accelerator includes a plurality of neural network dies, each neural network die including a respective plurality of tiles, each tile has input and output connections. The three-dimensionally stacked neural network accelerator is configured to process inputs by routing the input through each of the plurality of tiles according to a dataflow configuration and modifying the dataflow configuration to route an output of a tile before the faulty tile in the dataflow configuration to an input connection of a tile that is positioned above or below the faulty tile on a different neural network die than the faulty tile.