3D AND Flash Memory Gate Stack Isolation Wall Leakage
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Solution Overview
Problem
3D AND flash memory devices face challenges with gate-induced drain leakage due to the overlap of gate layers with drain pillars, which affects operational efficiency and reliability.
Innovation Solution
The implementation of a 3D AND flash memory device structure where isolation walls are buried in the gate layers, preventing overlap with drain pillars and reducing gate-induced drain leakage by ensuring the gate layer does not cover the drain pillar, thereby minimizing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate layers are stacked over channel pillars to form 3D memory structure, then memory integration and storage capacity are improved, but gate induced drain leakage increases due to overlap with drain pillars
Solution Approach 1:
The patent divides the gate stack structure into segmented regions by introducing isolation walls that partition the gate layers. These isolation walls create distinct zones: regions where gate layers contact channel pillars (for memory function) and regions where gate layers are isolated from drain pillars (to prevent leakage). This segmentation allows the structure to simultaneously achieve high integration through vertical stacking while eliminating harmful leakage paths through spatial separation.
Solution Approach 2:
The isolation wall acts as an intermediary element between the gate layers and drain pillars. It is positioned at the interface where these structures would otherwise overlap and cause leakage. The isolation wall material (typically dielectric) serves as a mediator that blocks the harmful electrical interaction while allowing both the gate stack and drain pillar to maintain their structural integrity and intended functions.
2Ease of manufacture
If gate layers overlap with drain pillars to simplify fabrication, then manufacturing complexity is reduced, but leakage current increases and device reliability deteriorates
Solution Approach 1:
The fabrication process segments the gate layer formation into controlled deposition zones. By using the isolation wall as a physical mask or boundary, the gate material is deposited only in desired regions (over channel pillars) while automatically preventing overlap with drain pillars. This maintains fabrication simplicity through self-aligned processes while ensuring reliable leakage prevention through precise spatial segmentation.
Solution Approach 2:
The isolation walls are formed in advance before gate layer deposition. This preliminary action establishes the boundaries that will guide subsequent gate material placement. By pre-positioning these protective structures, the fabrication process inherently prevents leakage paths without requiring complex post-processing or alignment steps, thus maintaining ease of manufacture while ensuring device reliability.
Data Source
AI summary
A 3D AND flash memory device includes a gate stack structure, a plurality of channel pillars, a plurality of first conductive pillars and a plurality of second conductive pillars, a plurality of charge storage structures, and a plurality of isolation walls. The gate stack structure is located on a dielectric substrate and includes a plurality of gate layers and a plurality of insulating layers alternately stacked on each other. The channel pillars pass through the gate stack structure. The first conductive pillars and the second conductive pillars are located in the channel pillars and are electrically connected to the channel pillars. The charge storage structures are located between the gate layers and the channel pillar. The isolation walls are buried in the gate layers and cover the charge storage structures at outer sidewalls of the second conductive pillars.