Solid-State Devices TRIZ Cases

A method fabricates magnetic memory patterns by performing thermal treatment and passivation layer formation simultaneously in one reactor.

Segmented sub-arrays with asymmetric angular orientations disrupt grid interference patterns, eliminating moiré artifacts without increasing chip size.

Lower refractive index films on top lenses position focal points above metal interconnects, preventing scattering and maintaining sensitivity.

Elevating backside transistor thresholds prevents interference and removes complex negative voltage generation needs.

A patterned electron blocking layer with thickness variations reduces leakage current to lower operation voltage while maintaining luminance intensity.

An in-package transmission line combiner resolves the efficiency-bandwidth trade-off by providing impedance inversion between transistor outputs.

Lateral wet etching expands the channel hole opening in 3D memory devices, reducing contact resistance caused by small punch etch areas.

An organic light emitting device uses an overhanging insulating layer to form electrically short-circuited electrodes without masks.

Cold stamping creates complex reflector shapes without expensive die casting, while Ni-Ag plating prevents layer lifting to ensure durability.

A transistor uses gradually shaped cavities filled with strain-inducing semiconductor alloys to enhance channel controllability.

Selective p-doping of the intermediate hole-transport layer improves device efficiency and lifetime while reducing dopant costs.

Differential sputtering creates recessed vias that provide visible alignment marks, reducing series resistance in MRAM arrays.

A nanostructure color filter integrates light guiding and color separation into a single layer to reduce image sensor thickness.

A retardation control film reverses circular polarization of external light reflected by the support plate in flexible displays.

Modular OLED panel cover connects multiple units via accessible contacts to eliminate resistive losses and maintain uniformity across large panels.

A semiconductor device uses a photomask with adjusted geometric center intervals to align contact and plug positions across stacked hierarchies.

An insulating matrix balances electron and hole injection in the quantum dot light-emitting layer, reducing background noise and autocorrelation coefficients.

A composite L-shape spacer prevents corner thinning in tunnel insulating layers, maintaining coupling ratio and read/write speed.

Vertical trench gates compress drift regions to shrink device size while maintaining punch-through withstand voltage.

A semiconductor device uses a light-transmitting conductive film as a capacitor electrode to increase charge capacity.

Segmented capping layers allow selective etching to expose metal pads, enabling defect correction without damaging microlenses.

A vertical channel transistor uses a sacrificial mandrel to support pillar patterns during gate electrode formation.

Metal plugs ground shields in backside illumination sensors, preventing charge accumulation and image saturation.

A silicon-based compound serves as a host material in organic light-emitting diodes to optimize energy levels.

Dual passivation layers with distinct dry etch rates enable single-mask patterning of oxide semiconductor thin film transistors.

A 3D-MIM-SHD capacitor employs a corrugated stack of conductive and dielectric layers to boost capacitance density by 10-36% within a compact footprint.

Through holes in the substrate dissipate heat and sweat from wearable devices, resolving the trade-off between thermal comfort and display area reduction.

A deep silicon via structure provides a low-inductance ground connection for power transistors.

A thin film transistor array uses a sheath-shaped source electrode surrounding the drain to reduce parasitic capacitance.

Asymmetric slope surfaces on the substrate redirect short wavelength light to direct vision, resolving limited color gamut in top-emitting displays.

A planarization insulating layer protrusion suspends a halftone mask above the pixel definition layer to prevent physical damage during fabrication.

A maskless wafer dicing method uses pre-formed undersurface grooves to guide plasma etching for precise substrate division.

Controlling the energy bandgap between P-type host and dopant levels balances charge injection, improving luminous efficiency and white balance stability.

A buried isolation pattern decouples the substrate from the active region in a semiconductor device.

A memory device page buffer unit selectively drives buffers based on cell counts to minimize error bits during read operations.

A reflection structure redirects light from a 1 to 20 μm high LED device through a substrate.

Segmented light emitting units with interstitial heat dissipation structures reduce burn-in risks while maintaining large-size visual effects.

Segmenting the phosphor layer into a remote carrier reduces thermal degradation and color shifting by isolating the conversion material from the LED chip.

Opposite-side placement of the photoelectric conversion part and transfer gate reduces noise while preventing BEOL contamination during fabrication.

Resin bonding layers harden to distribute fluorescent particles uniformly, eliminating color irregularities in light emitting devices.

A terminal electrode with a stepped surface increases contact area with anisotropic conductive film, preventing flexible printed circuit substrate peeling.

Self-healing polymer layers repair display surfaces to prevent glass shard escape and reduce glare without compromising optical transmission.

Silicon dioxide passivation layers reduce interface trap densities in vertical silicon active layers.

Bond light-emitting elements to a transmission member and form alignment marks based on captured images for precise contact positioning.

Voltage scanning with incremental limit currents removes defects in chalcogenide materials, increasing on/off ratio without doping complexity.

A light-emitting element uses a host material with a lower triplet level than the guest material to transfer energy.

An inner dam and concave-convex pattern seal a through-hole in the display area, blocking moisture permeation while preserving the light emitting layer.

An integrated bed-side battery and antenna eliminate cable obstructions in operating rooms while maintaining reliable wireless transmission of radiation images.

Stacked vertical memory arrays arrange NAND strings above one another to reduce die area while maintaining sensing margins.

Segmented AlGaN/AlN quantum wells resolve lattice mismatch dislocations to boost external quantum efficiency below 240 nm.