Vertical Silicon Active Layer Passivation for 3D Memory Integration
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Solution Overview
Problem
Conventional two-dimensional semiconductor memory devices face limitations in increasing integration due to high manufacturing costs and the need for expensive equipment to form fine patterns, while three-dimensional devices require reliable process technologies to achieve high integration at lower costs per bit.
Innovation Solution
The method involves forming a vertical stack of nonvolatile memory cells on a substrate by creating a silicon dioxide passivation layer on the sidewalls of a silicon active layer using thermal or radical oxidation processes, and forming a buried insulating pattern directly on this passivation layer to reduce crystalline defects and interface trap densities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional semiconductor memory devices are used, then manufacturing equipment cost is high, but integration is limited
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional vertical stacking of memory cells. Multiple memory cells are stacked vertically along the channel length, enabling higher integration density without requiring finer lateral patterning that would demand expensive equipment.
2Manufacturing precision
If three-dimensional semiconductor memory devices are manufactured, then integration increases, but process reliability is compromised
Solution Approach 1:
The patent applies different surface treatments to different sidewalls of the vertical channel. The first sidewall receives a standard dielectric layer, while the second sidewall undergoes oxidation treatment to form a silicon oxide layer, reducing interface trap densities and improving electrical characteristics locally where needed.
Solution Approach 2:
The patent performs oxidation treatment on the second sidewall of the vertical channel before forming the buried insulating pattern. This preliminary oxidation reduces crystalline defects and interface trap densities in advance, ensuring reliable electrical characteristics before subsequent manufacturing steps.
3Manufacturing precision
If fine patterns are formed in two-dimensional devices, then integration increases, but equipment cost increases
Solution Approach 1:
The patent achieves higher integration by stacking memory cells vertically rather than reducing lateral pattern dimensions. This vertical stacking approach increases integration density without requiring the expensive fine-patterning equipment needed for continued lateral scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances charge mobility and improves the electrical characteristics of three-dimensional semiconductor memory devices by reducing interface trap densities and defects, thereby increasing integration while lowering manufacturing costs.
Implementation Method 1
exposing the second sidewall with an oxidizing species that converts a surface of the second sidewall into a silicon dioxide passivation layer
Implementation Method 2
converting the second sidewall of the silicon active layer into a silicon dioxide passivation layer using a dry thermal oxidation process. In particular, the treating may include converting the second sidewall of the silicon active layer into a silicon dioxide passivation layer using an O2, O2/N2 and/or O2/N2O gas in a dry thermal oxidation process.
Implementation Method 3
Alternatively, the treating may include converting the second sidewall of the silicon active layer into a silicon dioxide passivation layer using a H2/O2 and/or H2O gas in a wet thermal oxidation process.
Implementation Method 4
the treating may include converting the second sidewall of the silicon active layer into a silicon dioxide passivation layer using a hydrogen gas, an oxygen gas and/or a hydrogen chloride gas in a radical oxidation process.
Data Source
AI summary
Methods of forming nonvolatile memory devices include forming a vertical stack of nonvolatile memory cells on a substrate. This is done by forming a vertical stack of spaced-apart gate electrodes on a first sidewall of a vertical silicon active layer and treating a second sidewall of the vertical silicon active layer in order to reduce crystalline defects within the active layer and/or reduce interface trap densities therein. This treating can include exposing the second sidewall with an oxidizing species that converts a surface of the second sidewall into a silicon dioxide passivation layer. A buried insulating pattern may also be formed directly on the silicon dioxide passivation layer.