3D-MIM-SHD Capacitor with Corrugated Stack for High Density
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Solution Overview
Problem
The semiconductor industry faces challenges in integrating high-density capacitors on a single chip for various functional circuits, such as mixed-signal, RF, and DRAM circuits, due to limitations in miniaturization and performance requirements for decoupling and noise filtering, which are not adequately met by traditional fabrication methods.
Innovation Solution
A method for forming a 3D-MIM-SHD capacitor involves depositing dielectric and conductive layers in recessed trenches on a semiconductor substrate, creating a corrugated stack with angled sidewalls, which increases capacitance and density while maintaining a small footprint, and forming contact plugs to connect these layers to active devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional 3-plate capacitors are used in metal layers, then fabrication is simple, but capacitance density is insufficient for high-performance applications
Solution Approach 1:
The patent transitions from planar 3-plate capacitors to 3D corrugated structures with angled sidewalls, adding vertical dimensionality to increase capacitance density. The corrugated stack creates multiple overlapping capacitor plates in three dimensions, effectively utilizing vertical space to achieve higher capacitance in a compact footprint.
Solution Approach 2:
The patent employs corrugated surfaces with curved or angled sidewalls instead of flat planar structures. The corrugated pattern creates increased surface area and overlapping regions between capacitor plates, enhancing capacitance density while maintaining a compact form factor suitable for modern semiconductor devices.
2Productivity
If minimum feature size is reduced for miniaturization, then integration density increases, but manufacturing precision requirements become more stringent
Solution Approach 1:
The patent divides the capacitor structure into multiple thin dielectric and conductive layers stacked in a corrugated configuration. This segmentation allows each layer to be formed with relaxed precision requirements compared to a single monolithic structure, while the cumulative effect of multiple layers achieves the desired high capacitance density.
Solution Approach 2:
The patent changes the geometric parameters of the capacitor structure by introducing corrugated patterns with specific angles and dimensions. By optimizing the corrugation angle, depth, and spacing, the design achieves high capacitance density while maintaining manufacturability with existing fabrication capabilities, effectively decoupling performance from extreme miniaturization.
Data Source
AI summary
Methods of forming a 3-dimensional metal-insulator-metal super high density (3D-MIM-SHD) capacitor and semiconductor device are disclosed herein. A method includes depositing a base layer of a first dielectric material over a semiconductor substrate and etching a series of recesses in the base layer. Once the series of recesses have been etched into the base layer, a series of conductive layers and dielectric layers may be deposited within the series of recesses to form a three dimensional corrugated stack of conductive layers separated by the dielectric layers. A first contact plug may be formed through a middle conductive layer of the corrugated stack and a second contact plug may be formed through a top conductive layer and a bottom conductive layer of the corrugated stack. The contact plugs electrically couple the conductive layers to one or more active devices of the semiconductor substrate.