MRAM Via Integration with Recessed Copper for Alignment
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Solution Overview
Problem
Current methods for forming vias in magnetoresistive-based devices, such as MRAM, result in high series resistance and alignment challenges due to opaque and planar top layers, which detract from the device's performance and reliability.
Innovation Solution
A method involving the formation of metal-filled vias with differential sputtering to create recesses in conductive and insulating materials, allowing for the precise placement of magnetic tunnel junctions and conductive electrodes, reducing series resistance and enabling alignment marks for subsequent processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional via formation methods are used, then vias can be formed in the interconnect stack, but the via resistance becomes high relative to the tunnel junction resistance
Solution Approach 1:
The patent changes the physical and chemical parameters of the via formation process by using atomic layer deposition (ALD) instead of conventional deposition methods. This enables precise control of via dimensions and material composition, achieving low via resistance while maintaining manufacturing precision. The ALD process parameters (temperature, pressure, precursor flow rates) are optimized to produce high-quality conductive fill with controlled resistance.
2Ease of manufacture
If the top layer is filled and polished to be completely planar, then step coverage is improved, but alignment marks become invisible for subsequent processing
Solution Approach 1:
The patent segments the via formation process into distinct stages: initial via etching, conductive material deposition, and selective removal. By segmenting the process, the patent can create the necessary topography for alignment mark visibility while still achieving adequate step coverage for MTJ material deposition. The via structure is divided into different depth zones with different material compositions.
Solution Approach 2:
Instead of completely filling and planarizing the via (conventional approach), the patent inverts the approach by intentionally leaving the via partially unfilled or by creating a recess structure. This inversion maintains alignment mark visibility while still providing sufficient conductive path for electrical connection, solving both the alignment and electrical performance requirements.
3Ease of manufacture
If the interconnect stack is coupled to the digit line landing pad at the same time the digit line is formed, then manufacturing is simplified, but the via resistance remains high
Solution Approach 1:
The patent performs preliminary actions by forming the via structure and depositing the conductive material before finalizing the digit line connection. This preliminary via formation allows optimization of the via resistance independently of the digit line formation process. The conductive material is deposited with controlled thickness and composition to ensure low resistance before the digit line is fully integrated.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces series resistance, improves robustness to dielectric breakdown, and allows for visible alignment marks, enhancing the placement of bit lines and overall device performance by creating a low-resistance path and avoiding shorts across the tunnel barrier.
Implementation Method 1
performing a sputter of the via and the first insulating material at different rates to form a recess comprising a first surface of the first via out of plane with a second surface of the first insulating material
Data Source
AI summary
A method is provided for forming a first via with an electrically conductive material, for example, copper, that is formed over and coupled to a conductive landing pad of an MRAM array. A sputter step is performed to lower the surface of the first via below that of a surrounding dielectric material. This recess is repeated in subsequent processing steps, providing alignment marks for the formation of a magnetic tunnel junction. The magnetic tunnel junction may be offset from the first via, and a second via being formed above the magnetic tunnel junction and to a conductive layer.