Deep Silicon Via Grounding for Power Transistor Inductance Reduction
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Solution Overview
Problem
High operating frequencies and currents in power transistors lead to voltage drops and thermal issues due to inductive bond wires and through-wafer vias, causing efficiency losses, thermal runaway, and mismatched amplifier conditions, which existing technologies struggle to address effectively.
Innovation Solution
A deep silicon via structure provides a low-inductance ground connection with tunable resistance, reducing semiconductor area usage and wafer backside processing complexity, allowing for improved power transistor performance and thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-wafer vias are used to provide ground connection, then inductance is reduced compared to bond wires, but the structure becomes very large and deep, consuming excessive semiconductor area
Solution Approach 1:
The invention divides the ground connection structure into multiple segments: shallow vias formed in the substrate and separate via plugs filled in the dielectric layer. This segmentation allows the ground connection to be distributed across multiple smaller structures rather than requiring a single large through-wafer via, thereby reducing the overall semiconductor area while maintaining low inductance performance
Solution Approach 2:
The invention transitions from a vertical through-wafer via approach to a hybrid approach combining shallow vertical vias in the substrate with horizontal via plugs in the dielectric layer. This dimensional change allows the ground connection to extend laterally, providing equivalent electrical performance with reduced footprint area
2Reliability
If through-wafer vias are used for grounding, then ground connection is achieved, but extensive backside processing is required which increases manufacturing complexity and cost
Solution Approach 1:
The invention performs preliminary actions by forming the shallow vias in the substrate before die attachment, and then filling via plugs in the dielectric layer after die attachment. This staged approach eliminates the need for extensive backside processing that would be required for through-wafer vias, simplifying manufacturing while achieving the same ground connection function
Solution Approach 2:
The invention inverts the conventional through-wafer via approach by forming vias only in the substrate portion rather than through the entire wafer including the die. The ground connection is then completed by filling via plugs in the dielectric layer, reversing the traditional sequence and eliminating complex backside processing steps
3Reliability
If conventional ballast resistors are used to prevent thermal runaway, then thermal stability is improved, but a large amount of semiconductor area is consumed
Solution Approach 1:
The invention merges the ballast resistor function with the via plug structure. The via plugs, which are necessary for ground connection, are configured to also provide the ballast resistance needed to prevent thermal runaway. This merging eliminates the need for separate ballast resistor structures, providing thermal stability while consuming minimal semiconductor area
Solution Approach 2:
The via plugs serve multiple functions simultaneously: providing ground connection, providing ballast resistance for thermal stability, and occupying minimal area. This multi-functionality allows a single structure to address multiple requirements that traditionally required separate components, thereby reducing overall semiconductor area consumption
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The deep silicon via structure achieves reduced inductance and resistance, enhancing power transistor efficiency, linearity, and reliability by providing a stable ground path and preventing thermal runaway, while being compatible with existing semiconductor manufacturing processes.
Implementation Method 1
the inductance of a bond wire creates a noticeable voltage drop
Implementation Method 2
these structures are too large and can not be used to provide a resistance at the ground node
Implementation Method 3
Due to the thermal properties of each power transistor, the current can be thermally hogged by one transistor
Data Source
AI summary
According to an exemplary embodiment, a semiconductor die including at least one deep silicon via is provided. The deep silicon via comprises a deep silicon via opening that extends through at least one pre-metal dielectric layer of the semiconductor die, at least one epitaxial layer of the semiconductor die, and partially into a conductive substrate of the semiconductor die. The deep silicon via further comprises a conductive plug situated in the deep silicon via opening and forming an electrical contact with the conductive substrate. The deep silicon via may include a sidewall dielectric layer and a bottom conductive layer. A method for making a deep silicon via is also disclosed. The deep silicon via is used to, for example, provide a ground connection for power transistors in the semiconductor die.