Oxide Semiconductor TFT Patterning with Differential Etch Passivation
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Solution Overview
Problem
The manufacturing of thin film transistors for display devices faces challenges due to the high cost and complexity associated with using multiple masks, particularly in forming polycrystalline silicon layers and oxide semiconductors, which require crystallization processes and increase manufacturing time and costs, while amorphous silicon transistors have low electron mobility.
Innovation Solution
A method for manufacturing a display substrate with a thin film transistor that involves forming a gate electrode, active pattern, source electrode, and drain electrode, using a first and second passivation layer with different etch rates for dry etching, and an annealing process to form a crack in the pixel electrode layer, reducing the number of masks needed and improving electron mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple masks are used to form polycrystalline silicon layers and oxide semiconductors, then manufacturing precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines multiple patterning steps into a single photolithography process by using a multi-layer structure (gate electrode, gate insulation layer, oxide semiconductor layer, etch stopper layer, data electrode layer) that can be patterned simultaneously. This merging of steps reduces the number of masks required while maintaining manufacturing precision through the careful design of layer interfaces and etch selectivity.
Solution Approach 2:
The patent segments the manufacturing process into distinct functional layers (gate electrode, gate insulation layer, oxide semiconductor layer, etch stopper layer, data electrode layer) that can be formed and patterned in a coordinated manner. This segmentation allows each layer to be optimized for its specific function while enabling simplified overall patterning through single-mask alignment.
2Reliability
If polycrystalline silicon is used for the active pattern, then electron mobility is improved, but manufacturing time and cost increase due to crystallization processes
Solution Approach 1:
The patent changes the material parameter from polycrystalline silicon to oxide semiconductor (such as IGZO - indium gallium zinc oxide). This material substitution maintains high electron mobility (comparable to polycrystalline silicon) while eliminating the need for high-temperature crystallization processes, thereby reducing manufacturing time and complexity.
Solution Approach 2:
The patent uses oxide semiconductor materials that can be deposited at low temperatures using simple sputtering or atomic layer deposition techniques, replacing expensive and time-consuming polycrystalline silicon crystallization processes. The oxide semiconductor layer serves as a disposable intermediate structure that enables high-performance transistors without requiring complex thermal processing.
3Ease of manufacture
If amorphous silicon is used for the active pattern, then manufacturing simplicity is improved, but electron mobility deteriorates
Solution Approach 1:
The patent uses composite material structures including oxide semiconductor layers (IGZO) combined with thin metal oxide layers (such as aluminum oxide or zinc oxide). This composite approach maintains the manufacturing simplicity of amorphous material deposition while achieving electron mobility characteristics closer to polycrystalline silicon through the specific composition and structure of the oxide semiconductor.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the reliability and electron mobility of thin film transistors while reducing manufacturing costs and time by simplifying the patterning process and utilizing oxide semiconductors, which can be easily formed in large scales at low temperatures.
Implementation Method 1
The removing the first passivation layer and the second passivation layer includes performing a dry etching process
Implementation Method 2
The dry etching process uses an etching solution having a higher etch rate with respect to the first passivation layer compared to an etch rate with respect to the second passivation layer
Implementation Method 3
an annealing process is further performed to form a crack in the pixel electrode layer before the removing the portion of the pixel electrode layer to form the pixel electrode
Data Source
AI summary
In a method for manufacturing a display substrate, a thin film transistor is formed on a base substrate. The thin film transistor includes a gate electrode, an active pattern, a source electrode and a drain electrode. A first passivation layer is formed to cover the thin film transistor. A second passivation layer is formed on the first passivation layer. A photoresist pattern is formed to partially expose the second passivation layer. The first passivation layer and the second passivation layer are partially removed to form a contact hole exposing the drain electrode. A pixel electrode layer is formed on the second passivation layer, the drain electrode and the photoresist pattern. A portion of the pixel electrode layer and the second photoresist pattern are removed to form a pixel electrode. The portion of the pixel electrode layer is disposed on a top surface and a sidewall of the photoresist pattern.