Stacked Vertical Memory Array Architectures for Reduced Die Area
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Solution Overview
Problem
As semiconductor memory technologies scale down, they face challenges in reducing semiconductor memory die area while maintaining sensing margins, particularly due to increased variability in memory cell I-V characteristics over process, voltage, and temperature variations.
Innovation Solution
The implementation of stacked vertical memory array architectures, where a first NAND string is formed above a second NAND string, with selective shorting of source lines, bit lines, and word lines to create low resistance paths, allowing for orthogonal arrangement to a substrate and varying string lengths to optimize memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional planar memory architectures are used, then manufacturing process is simpler, but memory die area is larger and sensing margins deteriorate
Solution Approach 1:
The patent transitions from conventional planar (2D) memory arrays to vertically stacked 3D memory arrays. Multiple memory arrays are stacked in the vertical dimension above a common substrate, with each array having memory cells oriented perpendicular to the substrate. This dimensional change increases storage density without proportionally increasing die area, as multiple arrays share common bit lines and source lines, effectively utilizing the third dimension for memory expansion.
Solution Approach 2:
The patent merges multiple memory arrays by sharing common bit lines and source lines across stacked arrays. Specifically, bit lines from upper arrays are connected to common bit lines, and source lines are shared among arrays, reducing the total number of interconnect lines required. This merging approach decreases overall device complexity and routing complexity while maintaining high storage density in the vertical stacking configuration.
2Manufacturing precision
If memory cell size is reduced to increase density, then more cells fit in given area, but I-V characteristic variability increases
Solution Approach 1:
The patent implements local quality by providing separate control mechanisms for different regions of the vertically stacked memory arrays. Word lines are independently controllable across different arrays, and select gates can be independently biased. This allows localized optimization of read and program operations for specific memory arrays or regions, compensating for process variations and maintaining consistent I-V characteristics across densely packed cells by adjusting parameters locally rather than relying on uniform global parameters.
3Area of stationary object
If vertically stacked memory arrays are implemented, then memory die area is reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent segments the vertically stacked memory structure into modular repeating units. Each memory array consists of repeating patterns of memory cells, word lines, and select gates that can be fabricated using standardized process modules. The vertical stacking is achieved through repeated deposition and patterning cycles that create identical or similar structural units at different heights. This segmentation into modular units simplifies manufacturing by allowing process reuse and reducing the complexity of fabricating entirely unique three-dimensional structures.
Data Source
AI summary
Systems and methods for implementing and using stacked vertical memory array architectures. A first NAND string may be formed or arranged above a second NAND string. The first NAND string may include a first drain-side select gate connected to a first set of memory cell transistors connected to a first source-side select gate. The second NAND string may include a second drain-side select gate connected to a second set of memory cell transistors connected to a second source-side select gate. The first NAND string and the second NAND string may comprise portions of the same or different memory array architectures (e.g., the first NAND string may be part of a memory array that uses U-shaped NAND strings and the second NAND string may be part of a memory array that uses single vertical NAND strings).