3D Memory Channel Hole Lateral Etch for Contact Resistance
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Solution Overview
Problem
The challenge in forming three-dimensional (3D) memory devices is the limited contact area between the channel structure and the epitaxial layer due to the small opening after a punch etch, leading to high contact resistance and under etch issues, which are exacerbated by the thickness of the SONO stack and small critical dimensions of the channel hole.
Innovation Solution
A method is introduced that includes forming an alternating dielectric stack, creating a channel hole, and then using a punch etch followed by a wet etch to expand the opening laterally, ensuring a larger contact area between the channel structure and the epitaxial layer, thereby improving electrical connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a punch etch is used to form an opening through the SONO stack, then the opening can be formed with precise depth control, but the opening area becomes too small leading to high contact resistance
Solution Approach 1:
The patent divides the opening formation process into two distinct stages: first a punch etch creates a controlled opening through the SONO stack, then a wet etch expands the opening laterally. This segmentation allows each process to optimize for its specific function - the punch etch for depth control and the wet etch for area expansion - thereby resolving the contradiction between precise depth control and sufficient contact area.
Solution Approach 2:
The punch etch is performed as a preliminary action before the wet etch expansion. By first creating a precisely controlled opening through the punch etch, the subsequent wet etch can reliably expand it without risking over-etching or loss of depth control. This preliminary action ensures that the final opening has both the required depth precision and sufficient area to reduce contact resistance.
2Productivity
If the SONO stack thickness is increased to improve memory density, then vertical integration is enhanced, but the opening formation becomes more difficult leading to under etch issues
Solution Approach 1:
The two-stage opening formation process segments the challenges of penetrating thick SONO stacks. The punch etch handles the initial penetration with precise depth control through the increased thickness, while the subsequent wet etch expands the opening laterally without requiring additional vertical etching. This segmentation prevents under-etch issues even as SONO stack thickness increases to improve memory density.
Solution Approach 2:
The patent transitions from purely vertical opening formation to include lateral expansion in the horizontal dimension. By using wet etch to expand the opening laterally after the punch etch creates the initial vertical opening, the process can accommodate increased SONO stack thickness without compromising opening depth control or creating under-etch issues.
3Productivity
If the channel hole critical dimension is reduced to increase memory capacity, then more channels can be packed, but the opening area becomes insufficient leading to high contact resistance
Solution Approach 1:
The opening formation is segmented into punch etch for initial opening creation and wet etch for lateral expansion. This allows the channel hole critical dimension to be reduced for increased memory capacity while the wet etch stage compensates by expanding the opening area laterally, maintaining sufficient contact area and low contact resistance despite the smaller channel dimensions.
Solution Approach 2:
The patent addresses the limited opening area in small critical dimension channel holes by adding lateral expansion through wet etch. This dimensional transition from vertical-only to lateral expansion allows sufficient contact area to be achieved even when channel hole critical dimensions are reduced to increase memory capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively enlarges the contact area between the channel structure and the epitaxial layer, reducing contact resistance and mitigating under etch issues, ensuring improved electrical connection and memory device performance.
Implementation Method 1
performing a wet etch to further remove a portion of the functional layer that is laterally extending on a top surface of the epitaxial layer
Implementation Method 2
performing a punch etch to remove the portions of the functional layer and the protecting layer that are laterally extending on a top surface of the epitaxial layer
Implementation Method 3
forming an epitaxial layer on a bottom of the channel hole
Data Source
AI summary
Embodiments of 3D memory devices and fabricating methods are disclosed. The method can comprise: forming an alternating dielectric stack on a substrate; forming a channel hole penetrating the alternating dielectric stack to expose a surface of the substrate; forming an epitaxial layer on a bottom of the channel hole; forming a functional layer covering a sidewall of the channel hole and a top surface of the epitaxial layer; forming a protecting layer covering the functional layer; removing portions of the functional layer and the protecting layer to form an opening to expose a surface of the epitaxial layer; expanding the opening laterally to increase an exposed area of the epitaxial layer at the bottom of the channel hole; and forming a channel structure on the sidewall of the channel hole and being in electrical contact with the epitaxial layer through the expanded opening.