Thin Film Transistor Array With Sheath Source Electrode
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Solution Overview
Problem
Existing thin film transistor arrays face issues with high gate-source capacitance, source-pixel capacitance, and gate-drain capacitance, leading to increased power consumption, display quality degradation, and potential short-circuits due to complex electrode geometries and angle portions that cause current concentration and defects.
Innovation Solution
A thin film transistor array design featuring a gate electrode, source electrode, and drain electrode with a semiconductor pattern and protection layer, where the drain electrode has a single linear shape, the source electrode has a linear and sheath shape surrounding the drain with a constant interval, and the source wiring is narrower than the semiconductor pattern width, reducing overlapping areas and capacitance, and the semiconductor pattern extends perpendicular to the gate wiring, covering the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex electrode geometries with angle portions are used, then electrode coverage and connection are improved, but current concentration and defects occur leading to reduced reliability
Solution Approach 1:
The patent applies curvature by replacing angle portions with arc portions in the electrode configurations. Specifically, the first electrode has arc portions at its ends, the second electrode has an arc portion at its end, and the third electrode has arc portions at its ends. This curvature design eliminates current concentration at sharp angles while maintaining proper electrode coverage and connections, thereby improving reliability without significantly increasing complexity.
2Strength
If larger overlapping areas between electrodes and wirings are used, then connection strength is improved, but gate-source capacitance and gate-drain capacitance increase leading to higher power consumption
Solution Approach 1:
The patent applies local quality by making the source wiring narrower than the semiconductor pattern width. This creates a localized reduction in overlapping area between the source wiring and the gate electrode, thereby reducing gate-source capacitance and power consumption. The connection strength is maintained through proper electrode design while the wiring is optimized to minimize parasitic capacitance in critical regions.
3Ease of manufacture
If source wiring width is increased to match semiconductor pattern width, then manufacturing simplicity is improved, but gate-source capacitance increases and display quality degrades
Solution Approach 1:
The patent applies local quality by differentiating the width of the source wiring from the semiconductor pattern width. The source wiring is intentionally made narrower to control gate-source capacitance at precision levels required for display quality. This deliberate width differentiation, while adding a manufacturing parameter, ensures precise capacitance control and prevents display quality degradation.
4Adaptability or versatility
If electrode configurations with multiple portions are used, then functional flexibility is improved, but device complexity increases and short-circuit risks arise
Solution Approach 1:
The patent applies curvature to simplify electrode configurations while maintaining functional flexibility. The arc portions at electrode ends eliminate the need for complex angle portions and multiple segments, reducing device complexity and short-circuit risks. The curved designs maintain proper electrical connections and functional flexibility through smooth transitions that preserve electrode effectiveness.
Data Source
AI summary
A thin film transistor array including a gate wiring connected to a gate electrode and extended in a first direction, a source wiring connected to a source electrode, a drain electrode having a gap from the source electrode, a semiconductor pattern formed at least in a portion corresponding to the gap between the source and drain electrodes, the semiconductor pattern having a region defined by extending the portion in a second direction perpendicular to the first direction, and a pixel electrode that overlaps with a capacitor electrode in the planar view. In the planar view, the drain electrode has a shape of a single line, the source electrode has a first portion in a line shape and a second portion in a sheath shape surrounding the drain electrode and keeping a space from the drain electrode, and the source wiring is narrower than the region of the semiconductor pattern.