Memory Device Page Buffer Control for Error Reduction

Solution Overview

Problem

Non-volatile semiconductor memory devices, such as flash memory, face challenges in reducing error bits during data processing operations, particularly in high-capacity and high-speed applications like smartphones, where power consumption and read/write reliability are critical.

Innovation Solution

A memory device with a memory cell array and page buffers that perform data processing operations by determining pre-charging, development, and latching operations, using processing circuitry to count on-cells and off-cells based on read voltage data, and selectively driving page buffers to minimize error bits and reduce power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If all page buffers are actuated during data sampling operations, then data reading speed is improved, but power consumption increases and error bits occur more frequently

Engineering Contradiction:

Improvedata reading speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The patent applies partial action by selectively actuating only the necessary page buffers during data sampling operations. The control circuit determines which page buffers need to be active based on the specific read operation requirements, rather than activating all page buffers. This reduces power consumption while maintaining adequate data reading speed by avoiding unnecessary buffer activations.

Inventive Principle:

Principle #16Partial or excessive action

2Speed

If all page buffers are actuated during data sampling operations, then data reading speed is improved, but error bits occur more frequently

Engineering Contradiction:

Improvedata reading speedVSAvoiderror bit occurrence

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent applies partial action by selectively actuating only the necessary page buffers during data sampling operations. The control circuit determines which page buffers need to be active based on the specific read operation requirements, rather than activating all page buffers. This reduces power consumption while maintaining adequate data reading speed by avoiding unnecessary buffer activations.

Inventive Principle:

Principle #16Partial or excessive action

3Use of energy by moving object

If selective page buffer actuation is implemented, then power consumption is reduced, but device complexity increases

Engineering Contradiction:

Improvepower consumptionVSAvoidcontrol circuit complexity

Core Design Contradiction:

Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent implements feedback through the control circuit that monitors read operation requirements and dynamically determines which page buffers should be actuated. The control circuit receives information about the current operation state and adjusts buffer activation accordingly, creating a feedback loop that optimizes power consumption based on actual operational needs while managing complexity through intelligent control logic.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS10600453B2Memory device

Publication Date: 2020.03.24 SAMSUNG ELECTRONICS CO LTD

AI summary

A memory device includes a memory cell array including a plurality of memory cells, a page buffer unit including the plurality of memory cells, and a driving determination unit determining whether to perform at least one of a pre-charging operation, a development operation and a latching operation of page buffers connected to the memory cells provided with the read voltage.