Vertical Channel Transistor Pillar Collapse Prevention

Solution Overview

Problem

The manufacturing process of vertical channel transistors is complex and prone to pillar pattern collapse or sticking, leading to reliability issues in semiconductor apparatuses due to the difficulty in forming and etching the gate electrode around pillar patterns.

Innovation Solution

A method involving sequential deposition of a gate electrode material and a sacrificial insulating layer, patterning to form holes, forming pillar patterns with a gate insulating layer, and using a spacer nitride material to enclose the pillar patterns, thereby preventing collapse and simplifying the manufacturing process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the lower portion of the pillar is recessed to form the surrounding gate electrode, then the gate electrode can be formed around the pillar, but the width of the lower portion becomes smaller and pillar collapse occurs

Engineering Contradiction:

Improvegate electrode formationVSAvoidpillar pattern stability

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent applies preliminary action by forming a mandrel structure with uniform width before creating the gate electrode. The mandrel is formed by depositing a first conformal layer and a second conformal layer sequentially, ensuring the lower portion maintains the same width as the upper portion. This preliminary structure prevents pillar collapse during subsequent gate electrode formation processes.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent uses an intermediary mandrel structure that acts as a temporary support during gate electrode formation. The mandrel, formed by conformal deposition layers, serves as a mediator between the pillar pattern and the surrounding gate electrode, maintaining structural integrity throughout the manufacturing process.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Ease of manufacture

If spacer etching is used to form the surrounding gate electrode, then the gate electrode can surround the recessed pillar, but the conductive layer is not clearly etched and pillar patterns are not separated

Engineering Contradiction:

Improvesurrounding gate electrode formationVSAvoidpattern separation clarity

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming a mandrel structure with uniform width before creating the gate electrode. The mandrel is formed by depositing a first conformal layer and a second conformal layer sequentially, ensuring the lower portion maintains the same width as the upper portion. This preliminary structure prevents pillar collapse during subsequent gate electrode formation processes.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent uses an intermediary mandrel structure that acts as a temporary support during gate electrode formation. The mandrel, formed by conformal deposition layers, serves as a mediator between the pillar pattern and the surrounding gate electrode, maintaining structural integrity throughout the manufacturing process.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method enhances the reliability of semiconductor apparatuses by preventing pillar pattern collapse and improving the manufacturing process complexity, ensuring stable and reliable vertical channel transistors.

Implementation Method 1

forming a gate insulating layer on the inner sidewall of the hole

Methodology Applied

Scientific EffectDeposition: Deposition (physical)

Implementation Method 2

forming a spacer nitride material on the semiconductor substrate from which the patterned sacrificial insulating layer is removed

Methodology Applied

Scientific EffectDeposition: Deposition (physical)

Data Source

PatentUS20150090951A1Semiconductor apparatus having vertical channel transistor and method of fabricating the same

Publication Date: 2015.04.02 SK HYNIX INC

AI summary

A semiconductor apparatus and a method of fabricating the same are provided. The method includes sequentially depositing a gate electrode material and a sacrificial insulating layer on a semiconductor substrate, patterning the gate electrode material and the sacrificial insulating layer to form one or more holes exposing a surface of the semiconductor substrate, forming a gate insulating layer on an inner sidewall of the hole, forming one or more pillar patterns each filled in the hole and recessed on a top thereof, forming a contact unit and an electrode unit on the pillar pattern, removing a patterned sacrificial insulating layer and forming a spacer nitride material on the semiconductor substrate from which the patterned sacrificial insulating layer is removed, and removing portions of the spacer nitride material and a patterned gate electrode material between the pillar patterns.