3D Back-End Active Transistor Structure for Higher Drive Current
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Solution Overview
Problem
The challenge in IC manufacturing is to improve back-end active devices to achieve sufficient drive current while avoiding thermal damage to front-end structures, which is limited by process temperature restraints.
Innovation Solution
The solution involves forming back-end active devices with a channel region that tracks a three-dimensional topography, allowing for two configurations: high drive current and low leakage. This is achieved by depositing a semiconductor layer over fin-shaped structures and forming gate structures with specific layers to optimize channel width and length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If back-end active devices are fabricated with larger geometry to achieve sufficient drive current, then drive current is improved, but space consumption at the FEOL level increases
Solution Approach 1:
The patent applies dimensionality change by transitioning from planar 2D channel structures to three-dimensional topography-tracking channel structures. The channel region conforms to the 3D shape of underlying fin-shaped interconnect structures, effectively utilizing vertical space and converting lateral area constraints into volumetric utilization. This allows larger effective channel width and drive current without increasing the device footprint at the FEOL level.
Solution Approach 2:
The patent implements nesting by placing the active device channel region within and conforming to the three-dimensional topology of the interconnect structure. The channel is nested within the fin-shaped structures formed by metal layers and dielectric materials, allowing the device to borrow the vertical dimension of the interconnect stack to achieve larger effective area without occupying additional lateral space.
2Power
If process temperature is increased to improve device performance, then drive current is improved, but thermal damage to front-end structures occurs
Solution Approach 1:
The patent applies segmentation by dividing the fabrication process into distinct temperature zones: FEOL processes performed at lower temperatures and BEOL active device fabrication performed at higher temperatures. This temporal and spatial separation allows each process stage to operate at its optimal temperature without causing damage to previously formed structures, as the sensitive FEOL structures are already complete and isolated before the high-temperature BEOL processing begins.
Solution Approach 2:
The patent implements preliminary action by completing all front-end-of-line structure fabrication before initiating back-end-of-line active device formation. This sequencing ensures that temperature-sensitive FEOL structures are already formed and protected before the higher temperature BEOL processes begin, preventing thermal damage while still allowing optimized processing temperatures for each stage.
Data Source
AI summary
Semiconductor structures and formation processes thereof are provided. A semiconductor structure of the present disclosure includes a semiconductor substrate, a plurality of transistors disposed on the semiconductor substrate and comprising a plurality of gate structures extending lengthwise along a first direction, a metallization layer disposed over the plurality of transistors, the metallization layer comprising a plurality of metal layers and a plurality of contact vias, a dielectric layer over the metallization layer, a plurality of dielectric fins extending parallel along the first direction and disposed over the dielectric layer, a semiconductor layer disposed conformally over the plurality of dielectric fins, a source contact and a drain contact disposed directly on the semiconductor layer, and a gate structure disposed over the semiconductor layer and between the source contact and the drain contact.