Solid-State Devices TRIZ Cases

Segmented reflective layers and direct common-electrode contact boost light output while lowering contact resistance and power use.

A reflective structure around micro LED sub-pixels improves electrical transmission and limits sidewall-related EQE loss during fabrication.

A 3D topography-tracking channel boosts back-end transistor drive current while limiting FEOL space use and thermal damage.

Parallel switch-diode fingers cut ESD protection area while preserving discharge protection for IC substrate and package pins.

A single insulation layer and via-linked touch electrodes cut parasitic capacitance and process steps in an In-Cell touch array substrate.

An optical element widens sub-display light angles so frame regions act as display areas, removing visible seams in spliced screens.

A multi-tier 3D interconnect module shortens wire bonds in tall die stacks to reduce wire sweep, signal delay, and crosstalk.

Offset multi-layer contact holes enlarge the pixel electrode-drain interface, lowering resistance and stabilizing electron transmission for higher-resolution displays.

Bonded active LED structures with insulating layers and conductive vias improve color gamut, series connection, and chip integrity in a compact footprint.

Sequential epitaxial growth in etched trenches builds RGB GaN LED arrays on one sacrificial layer, cutting process complexity and cost.

Shared package walls suppress side emission and improve blue, red, and green light mixing for better color balance with easier red generation.

Segmented encapsulation on a 3D display baseplate protects emitters and drive circuits while improving light direction and splicing-gap appearance.

Selective area growth forms electrically isolated micro LEDs without perimeter etching, reducing surface recombination and improving light emission.

Electric fields align light emitting elements during deposition, improving substrate placement accuracy without complex mechanical alignment.

Asymmetric bump and recess features guide multi-color micro LEDs into place quickly, improving placement accuracy and preventing color mixing.

An encapsulated LED chip array with shared parallel wiring enables smaller packages while preserving light output, connectivity, and lower optical crosstalk.

Vertically staggered overlapping mesas remove the external panel, shrinking micro LED pixel size while preserving transmittance and emitting area.

Stacked quantum-effect sensing layers extend quantum length in photodiodes, improving sensitivity, energy conversion, yield, and reliability.

Passive deflector arrays with tuned diameters and spacing steer selected wavelengths at target angles, improving display color separation and imaging.

Using a two-transistor W/L ratio where W2/L2 ≥ W1/L1 suppresses kink effects, stabilizes OP-AMP current output, and lowers power use.

A grid electrode layer combines touch sensing and LED connections in one slim stack, preserving transparency while reducing assembly thickness.

Movable conductive particles switch the data line and pixel electrode connection to avoid TFT parasitic capacitance and prevent image sticking.

Varying scattering patterns across pixel units breaks periodicity that causes flare while preserving light capture and manufacturing efficiency.

Face-to-face hybrid bonding links top metal layers through via ladders, enabling dense 3D SoC interconnects with timing closure.

Staggered micro LED mesas use bottom connections on an IC backplane to keep emitting area large while reducing pixel dimensions.

Insert-fit chip and substrate electrodes enable micro-LED backplane repair without heating or welding, reducing cost and protecting nearby joints.

A hybrid substrate joins SOI and bulk silicon regions so RF and digital or analog devices can be built together with lower yield loss and routing cost.

A lower-doped middle buried-layer section raises ESD breakdown voltage in a PNP protection cell without increasing die area or resistance.

Abrasive-particle grooving in the glass bending area helps bendable displays cut non-display area while reducing substrate breakage.

Multiple avalanche diode paths with independent breakdown settings improve high-speed ESD protection while keeping dynamic resistance low.

Combining LED pixels, VCSEL emitters, and photodetectors on one substrate enables visible display output plus infrared sensing for motion and face capture.

Direct bonding of optoelectronic and control circuits enables 3D LED color emission without wavelength conversion, reducing complexity and loss.

Substrate protrusions embedded in a ring-shaped wall lengthen the moisture path and strengthen sealing around the sensor chip.

Low-temperature top-layer transistor formation and alignment-aware bonding improve 3D chip connection density without damaging lower wiring.

A recessed base substrate embeds the imaging module under the display to improve light transmittance, sealing, and screen-to-body ratio.

By extending the light emitting layer beyond conductive layer edges, this micro-LED layout cuts surface recombination and improves isolation.

Interdigital Schottky photodiodes in a display panel improve photocarrier collection and photoelectric responsivity for full-screen fingerprint sensing.

DNA origami positions quantum dots with nanometer precision, breaking 200 PPI printing limits for AR and VR display substrates.

Scatter reflection portions above light sources improve luminance uniformity in thin direct-type LCD backlights while preserving high contrast.

A dual-region high-index grating boosts guided-mode resonance to reflect target wavelengths more strongly and suppress unwanted light in displays.

A surface-modified PEDOT:PSS and dual hole auxiliary layers improve energy alignment, hole transport, and quantum dot device lifespan.

Adjacent pixel transistors share an active region to cut isolation trench area, reducing pixel pitch while preserving signal integrity.

A spacer on the data-line alignment part prevents alignment-film scratches during pressure tests, reducing light leakage in LCD panels.

An embedded infrared-absorbing release layer enables rapid SOI substrate thinning without grinding, polishing, or etching damage.

An active hole and overlapping conductive layer shield the TFT channel from hydrogen and light to suppress threshold voltage shift.

A low-silicon interfacial region in the oxide semiconductor film limits impurities, improves crystallinity, and stabilizes transistor behavior.

A two-stage ESD routing scheme links I/O pad clusters across wafer and packaging stages while preserving die edge area for higher IC density.

A resonance cavity between N-type and P-type semiconductor layers boosts micro LED light emission through multiple reflections and lower metal absorption.

An ITO blocking member stops glue from reaching the light-transmitting area while preserving electrical connection and camera image quality.

Transfer control circuits swap channel commands and data words to offset interface mismatch and reduce skew in stacked chips.

A doped semiconductor collimator for contact image sensors aligns incident light while absorbing ambient infrared noise in a compact, lower-cost structure.

A widened gate line with a recess cuts resistance and TFT drain overlap capacitance, reducing signal delay in large LCD array substrates.

Stacked and folded memory elements share a common node to cut parasitic capacitance, reduce charge disturbance, and improve data retention.

A thin metal shielding film inside the insulating layer blocks external electric fields while maintaining light transmission and emission stability.

Vertical fan-in wire bonding links stacked memory dice while saving package board space and supporting dense memory package interconnections.

Condensing components redirect sub-pixel light in a color film substrate to reduce total reflection and improve front-view brightness.

Separating power pads, fan-out lines, and integrated bus lines cuts overlap and contact failures while keeping pixel power delivery stable.

A thick protection dielectric layer covers sharp trench corners to buffer stress, preventing electrode cracking in high-density semiconductor capacitors.

Varying nanopattern diameters across the wafer compensates composition drift and keeps light-emitting elements in the same wavelength band.

A dual barrier metal and oxide sequence lowers contact resistance while limiting hydrogen absorption that shifts MOS threshold voltage.

Embedded gaps between nanowire semiconductor layers reflect or scatter lateral light upward, boosting top-surface emission without added package complexity.

Machine learning selects donor coupons and offsets to fill microLED substrate vacancies in fewer parallel transfer steps, improving yield.

Interface doping with P-type or Group VIIA materials passivates the Ge-Si boundary to curb electron leakage and lower dark current.

A rigid-flex chip packaging structure matches thermal expansion to improve bonding precision and increase output channels for high-resolution 3D displays.

A pad-overlapping protective layer creates a step-free board surface, reducing lifting and compression defects in display assembly.

A metal layer embedded at the opening lowers transparent electrode impedance, hides reflection, and increases display aperture ratio.

A fluorine concentration gradient beside the insulating layer helps etched light-emitting elements suppress defects and preserve emission efficiency.

Shield lines and dummy pads in an IC bonding layer cut pad-to-pad inductive and capacitive crosstalk, supporting higher image resolution.

Misplaced light emitters create electrode step differences; this case removes them outside emission areas to prevent disconnection and improve reliability.

Alternating low- and high-index capping layers improve OLED moisture sealing while directing more light toward the display surface.

A shared gate coupled to negative and positive carrier channels flattens capacitance, reducing AM-AM and AM-PM distortion in RF amplifiers.

Selective absorbing films remove unbound paste constituents to raise particle density and reduce outgassing or leaching in electronic thin films.

A non-interlaced stacked 8-shaped coil layout cuts parasitic capacitance while preserving symmetry, small area, and a higher quality factor.

Waste heat from steam pipes is converted by a clamp-mounted thermoelectric generator into maintenance-free power for remote sensors.

Flexible films and matched-expansion buffer sheets protect deposition masks from transport stress and thermal warping, preserving mask accuracy.

A diffusion member evens incident light angles before wavelength conversion, reducing backlight color unevenness and improving luminance uniformity.

Stacked LED units and a color conversion layer create full-color micro-LED pixels on one substrate, avoiding mass transfer for high-resolution displays.

A junction separation trench blocks dopant diffusion between diode junctions, improving electrical characteristics and breakdown voltage stability.

Trenched insulating layers and conductive pillars spread LED current more evenly, improving brightness uniformity, adhesion, and yield.

Light-scattering trenches extend photon paths in SPAD image sensors, improving low-light sensitivity, signal-to-noise ratio, and depth sensing.

Sidewall reflectors redirect in-plane emission from columnar semiconductor layers toward the main surface, reducing absorption and improving quantum efficiency.

Common electrode wirings placed between adjacent pixel electrodes strengthen edge electric fields, reducing LCD dark stripes and improving transmittance.

A moat, dual-index planarization layers, and a reflective plate redirect lateral LED light to raise front luminance and reduce bank absorption.

A nickel-alloy anti-oxidation layer protects thick copper wiring in Mini LED display substrates while avoiding costly ENIG processing.

Controlled phosphine doping and selective ohmic-layer etching suppress TFT semiconductor protrusions, improving panel uniformity and stability.

Specialized RGB, yellow, and NIR pixels with NIR cut filtering improve low-light sensitivity while preserving color accuracy and contrast.

Trench-anchored passivation confines bonding material during thermal compression, preventing shorts and improving sub-pixel attachment reliability.

Contacts placed within each LED unit free lateral pixel space, boosting micro-display brightness while preserving independent drive and isolation.

Larger confinement wells and guided droplet spreading improve inkjet OLED layer uniformity, fill factor, and display lifetime.

An antiparallel PN diode is tuned to avalanche before GaN HEMT drain-source overvoltage causes destructive breakdown.

Parallel metal connections in the non-display area cut line resistance, enabling narrower borders and higher refresh rates without extra photomasks.

Pre-formed slits in a heat-treated wavelength conversion layer contain adhesive between closely spaced light-emitting elements and preserve optical performance.

A recess pattern in the transparent connection electrode relieves stress, prevents cracking, and preserves electrical reliability in micro-LED displays.

Combining two photodetector outputs with shifted peaks and opposite signal changes shortens falling time for faster optical communication.

Two LED sources with tuned wavelengths and phosphor mixing control melanopic ratio while keeping efficient white light near the blackbody locus.

Cast OGS scintillators with polymer or plasticizer additives avoid machining damage in high-aspect-ratio radiation detectors.

Patterned InAlGaN seed regions let InGaN layers relax with different lattice parameters, reducing defects for multi-color LEDs and LDs.

Segmented transparent and metal wiring lets an under-display sensor region pass light while preserving low-resistance signal transmission.

An integrated electrode layout adds pressure sensing to touch input, helping displays distinguish input and non-input sections more accurately.

Direct flip-chip mounting on a transmissive support removes wire bonds, saving space while improving SSRT connection reliability and heat dissipation.

Different side-surface conductor resistances preserve signal transmission while reducing panel bending space and visible tile gaps.

Separate gate insulator thicknesses let driving and switching TFTs balance grayscale control and fast switching in OLED display panels.

A segmented dam structure raises encapsulation where needed while preserving light transmittance for under-display optical devices.

A lens material layer fills substrate isolation trenches and doubles as a pad etch mask, cutting masks and process steps in image sensor fabrication.

A higher-bandgap dielectric around capacitor grain sidewalls blocks DRAM leakage paths while preserving thin equivalent oxide thickness.

A convex hemispherical nitride structure with passivation limits etch sidewall damage, improves alignment, and boosts micro-LED efficiency.

Alternating transparent oxide and light-transmitting metal films cut electrode reflection, improving micro-LED contrast and dark-pixel appearance.

Alternating NMOS and PMOS layers with a shared gate layout increases CMOS density and improves wiring flexibility in stacked semiconductor circuits.

Distinct substrate regions, local masks, and trench isolation let logic, high-voltage, and memory devices be fabricated together with less cross-regional interference.

Bank-divided sub-areas and organic-layer openings help equalize light emitting element distribution and reduce display luminance deviation.

Different etch rates in a multilayer gate layer suppress sidewall protrusions, reducing short-circuit risk and preserving capacitor voltage.

Sidewall and contact isolation layers in a 3D NAND staircase prevent word-line leakage and punch-through during contact hole wet etching.

Bottom-side fanout routing and side wiring let Micro LED pixels reach the substrate edge, shrinking tiled display gaps to about one pixel.

Inclined grooves in the camera region place transparent wirings on groove walls to preserve light transmittance and ease high-PPI routing.

Layered green-yellow and red photoluminescence over blue LEDs improves white LED efficacy, color stability, and phosphor use.

Pre-formed select gate conductors reinforce tiered 3D NAND stacks, preventing insulating-layer bending during slit and opening formation.

A concave reflector embedded in the ILD redirects and focuses incident radiation back to the photodetector, improving quantum efficiency and limiting crosstalk.

Color adjustment patterns are cured on micro-LED light-emitting areas before transfer, improving placement yield, durability, and light extraction.

Cavities in a Si-based phosphor binder improve micro-LED pixel contrast and lumen output while preserving particle stability.

Asymmetric grid sidewalls around color filters cut excess green light and balance sensor sensitivity for better image representation and HDR.

Refraction structures redirect LLO laser energy away from bonding regions, enabling RGB LED transfer without backplane damage.

A multilayer gate and protruding isolation structure improve 3D memory integration while limiting voids, etch damage, and process instability.

Staged removal of partially sacrificial layers keeps insulative tiers supported, preventing void closure during 3D NAND gate formation.

A multi-step wafer grinding and femtosecond laser process removes surface and internal cracks to improve semiconductor reliability.

Fewer protective layers on the scintillator light-emission surface cut scattering while other surfaces retain moisture resistance.

RGB micro-LEDs are grown on one substrate using porosity-controlled regions, avoiding wafer alignment and color conversion layers.

Center-shifted micro-lens peaks in shared pixels improve autofocus signal contrast while preserving light delivery to the right photodiodes.

Nd2(Si, Ti, Ge)2O7 particles narrow display light spectra by absorbing specific wavelengths, improving color reproduction and purity.

An oxide TFT array with a light shielding pattern and doped gate raises threshold voltage, blocks off-state leakage, and improves low-gray display control.

By overlapping the vertical scan wire, the common electrode shields pixel electrodes to reduce parasitic capacitance and LCD crosstalk.

A five-patterning self-aligned array substrate process cuts oxide TFT mask count while preserving alignment, insulation, and stability.

Using Group 11 metal chalcogenides in the hole transport region improves hole injection, lowers driving voltage, and extends light-emitting device life.

Adjustable UV and visible LED wavelength, intensity, and timing increase beneficial phytochemicals in cultivated plants without harming growth.

Sidewall reflective layers in bank openings redirect lateral LED emission toward the output direction, increasing light extraction efficiency.

A quantum dot light-converting layer tunes blue-to-green spectral ratios to reach DCI-P3 green output with simpler color temperature adjustment.

Pixels linked to multiple controllers cut data rates on large display substrates while preserving high-resolution output.

Variable tunnel oxide thickness follows memory hole diameter to widen the threshold window and reduce read disturb in stacked semiconductor memory.

A conductive film linked to a shielding layer drains cover-plate static electricity, preventing green shift and four-split screen faults.

Photosensitive areas embedded between OLED pixels expand fingerprint unlocking across the screen while lowering module cost.

A stacked auxiliary charge holding section boosts global shutter pixel capacity without enlarging pixel area, helping preserve image quality.

Switchable capacitors and dual photodiodes expand dynamic range, improve low-light SNR, and reduce image sensor noise.

A curved chip structure bends the luminous layer to widen near-eye field of view, reduce edge distortion, and improve image uniformity.

An oxidation region on a bulk semiconductor substrate enables SOI-like FinFET isolation, cutting wafer cost while reducing leakage and capacitance.

A boron-coated back-thinned SOI sensor uses a p-type gradient to boost deep UV sensitivity while protecting CMOS circuits from thermal damage.

Tapered trench isolation improves peripheral high-voltage operation while keeping memory-array pitch and reducing fabrication steps.

A transparent-plate package replaces TSVs with redistribution layers, adhesive sealing, and conductive structures to cut sensor size and process cost.

A two-stage amplifier with capacitor offset feedback and separate resets cuts kTC noise and output offset in global shutter imaging.

Organic and inorganic capping layers shield quantum dots from light and oxygen, preserving color conversion efficiency and image quality.