TVS Clamping Element With Buried Structures
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Solution Overview
Problem
Conventional monolithic integration of Transient Voltage Suppressor (TVS) circuits faces challenges in combining high current handling with fast response requirements, leading to undesirable design compromises and inferior performance compared to hybrid integration methods.
Innovation Solution
The use of three epitaxial layers and two buried structures allows for optimized doping levels and thicknesses, enabling the monolithic integration of TVS clamping elements and auxiliary devices without significant compromise, with the TVS clamping element featuring a continuous high-doping region and the auxiliary device having a p-n junction formed by the top two epitaxial layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional monolithic integration is used with two epitaxial layers and a single buried structure, then manufacturing complexity is reduced, but performance is compromised due to inability to optimize both high current handling and fast response simultaneously
Solution Approach 1:
The device is segmented into three distinct epitaxial layers (first, second, and third) with different doping types and concentrations, allowing independent optimization of different functional regions. The clamping element and auxiliary elements are spatially segmented to have different structural configurations, enabling each to be optimized for its specific function without compromise.
Solution Approach 2:
Different regions of the device have locally optimized properties: the clamping element region has a continuous high-doping concentration path from substrate through all epitaxial layers for low resistance and high current handling, while the auxiliary elements region has lower doping concentrations in the second and third epitaxial layers for fast response and low capacitance. The buried structures are selectively positioned to provide local doping enhancement where needed.
2Speed
If epitaxial layer thickness is increased to prevent dopant diffusion perturbation in auxiliary devices, then fast response is improved, but manufacturing precision requirements increase
Solution Approach 1:
The first epitaxial layer is grown with sufficient thickness before subsequent processing steps to pre-establish a barrier that prevents dopant diffusion from the substrate from significantly perturbing the auxiliary device junctions. This preliminary structural preparation ensures that later thermal processing and doping steps do not compromise the fast response characteristics of the auxiliary elements.
3Power
If doping concentration is increased in TVS clamping element to reduce resistance, then current handling is improved, but capacitance increases which slows response time
Solution Approach 1:
The doping concentration is locally optimized for different device regions: the TVS clamping element has high doping concentration (5e16 cm−3 or greater) in a continuous region extending from the substrate through the epitaxial layers to achieve low resistance and high current handling, while the auxiliary elements have lower doping concentrations in their depletion regions to maintain fast response and low capacitance. This spatial differentiation of doping profiles resolves the contradiction between power handling and speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of high-performance TVS arrays with low capacitance and low resistance, eliminating the need for hybrid integration and reducing assembly costs while maintaining performance comparable to discrete diode designs.
Implementation Method 1
Thermal processing resulting in diffusion from the substrate and from the buried structures such that a single continuous region of high doping is formed by diffusion that extends from the substrate up to the top epitaxial layer
Data Source
AI summary
Monolithic integration of low-capacitance p-n junctions and low-resistance p-n junctions (when conducting in reverse bias) is provided. Three epitaxial layers are used. The low-capacitance junctions are formed by the top two epitaxial layers. The low-resistance p-n junction is formed in the top epitaxial layer, and two buried structures at interfaces between the three epitaxial layers are used to provide a high doping region that extends from the low-resistance p-n junction to the substrate, thereby providing low resistance to current flow. The epitaxial layers are lightly doped as required by the low-capacitance junction design, so the buried structures are needed for the low-resistance p-n junction. The high doping region is formed by diffusion of dopants from the substrate and from the buried structures during thermal processing.